JPS6428741A - Retrial system at branching - Google Patents

Retrial system at branching

Info

Publication number
JPS6428741A
JPS6428741A JP62183737A JP18373787A JPS6428741A JP S6428741 A JPS6428741 A JP S6428741A JP 62183737 A JP62183737 A JP 62183737A JP 18373787 A JP18373787 A JP 18373787A JP S6428741 A JPS6428741 A JP S6428741A
Authority
JP
Japan
Prior art keywords
register
retrial
instruction
period
processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62183737A
Other languages
Japanese (ja)
Inventor
Kunihiro Torikawa
Katsuyuki Iwata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP62183737A priority Critical patent/JPS6428741A/en
Publication of JPS6428741A publication Critical patent/JPS6428741A/en
Pending legal-status Critical Current

Links

Landscapes

  • Retry When Errors Occur (AREA)
  • Executing Machine-Instructions (AREA)

Abstract

PURPOSE:To eliminate the processing period incapable of retrial by using a branch destination instruction as an instruction to apply retrial during the retrial processing period corresponding to a no processing operation period. CONSTITUTION:Access is started by a storage address E0 in a storage device 20 at a processing period T-2 and the E0 is set to a register 22. An instruction by the E0 is fetched in a register 32 via a selector 31 at a period T-1 to form a branch instruction. simultaneously, it is set to a register 23. A branch instruction E0 is set to a register 24 via a selector 26 and the E0 is read from the register 23 to obtain a storage address B0 in the device 20 and set to the register 21 via a selector 27. Successful branching and the latch 33 are ORed (35) at periods T1, T2 and an ineffective processing instruction NOP is given to the register 32 to form a non processing period. If an error is detected for a period T3 and a retrial request exists, the retrial is executed by a branch instruction B0 read from the device 20.
JP62183737A 1987-07-24 1987-07-24 Retrial system at branching Pending JPS6428741A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62183737A JPS6428741A (en) 1987-07-24 1987-07-24 Retrial system at branching

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62183737A JPS6428741A (en) 1987-07-24 1987-07-24 Retrial system at branching

Publications (1)

Publication Number Publication Date
JPS6428741A true JPS6428741A (en) 1989-01-31

Family

ID=16141091

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62183737A Pending JPS6428741A (en) 1987-07-24 1987-07-24 Retrial system at branching

Country Status (1)

Country Link
JP (1) JPS6428741A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5920055A (en) * 1982-07-26 1984-02-01 Fujitsu Ltd Retrial system of branch instruction

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5920055A (en) * 1982-07-26 1984-02-01 Fujitsu Ltd Retrial system of branch instruction

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