JPS5748140A - Optional address branching system of computer - Google Patents

Optional address branching system of computer

Info

Publication number
JPS5748140A
JPS5748140A JP55122579A JP12257980A JPS5748140A JP S5748140 A JPS5748140 A JP S5748140A JP 55122579 A JP55122579 A JP 55122579A JP 12257980 A JP12257980 A JP 12257980A JP S5748140 A JPS5748140 A JP S5748140A
Authority
JP
Japan
Prior art keywords
program
address
cpu
memory
branch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55122579A
Other languages
Japanese (ja)
Inventor
Tsuneyoshi Muranaka
Okifumi Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ricoh Co Ltd
Original Assignee
Ricoh Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ricoh Co Ltd filed Critical Ricoh Co Ltd
Priority to JP55122579A priority Critical patent/JPS5748140A/en
Publication of JPS5748140A publication Critical patent/JPS5748140A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
    • G06F9/30054—Unconditional branch instructions

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)

Abstract

PURPOSE:To execute debug and check service swiftly and exactly, by executing a branch to an address prescribed in advance, irrespective of a program, at an optional point, when the program is proceeding, and also saving the contents of the program before the branch operation is executed. CONSTITUTION:A central processing equipment CPU reads out a data from an address designated to a memory 2, by setting an address ADR in order to a program counter 1. A device 10 monitors an operation of the CPU, checks an output of a coinciding circuit by a branch controlling circuit only when a program is read from the memory 2, switches an address link to the memory, to the device 10 from the CPU when it has coincided with a branch address and contents of a register 5, reads a program of the memory 2 irrespective of an address line of the CPU, and transfers it to the CPU.
JP55122579A 1980-09-04 1980-09-04 Optional address branching system of computer Pending JPS5748140A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55122579A JPS5748140A (en) 1980-09-04 1980-09-04 Optional address branching system of computer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55122579A JPS5748140A (en) 1980-09-04 1980-09-04 Optional address branching system of computer

Publications (1)

Publication Number Publication Date
JPS5748140A true JPS5748140A (en) 1982-03-19

Family

ID=14839397

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55122579A Pending JPS5748140A (en) 1980-09-04 1980-09-04 Optional address branching system of computer

Country Status (1)

Country Link
JP (1) JPS5748140A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0376255A2 (en) * 1988-12-27 1990-07-04 Kabushiki Kaisha Toshiba Method and apparatus for controlling branching

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0376255A2 (en) * 1988-12-27 1990-07-04 Kabushiki Kaisha Toshiba Method and apparatus for controlling branching

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