JPS5533243A - Data transfer control system - Google Patents

Data transfer control system

Info

Publication number
JPS5533243A
JPS5533243A JP10606978A JP10606978A JPS5533243A JP S5533243 A JPS5533243 A JP S5533243A JP 10606978 A JP10606978 A JP 10606978A JP 10606978 A JP10606978 A JP 10606978A JP S5533243 A JPS5533243 A JP S5533243A
Authority
JP
Japan
Prior art keywords
signal
channel
input
output device
disconnected
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10606978A
Other languages
Japanese (ja)
Other versions
JPS599927B2 (en
Inventor
Hitoshi Kaminomura
Koji Hayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP53106069A priority Critical patent/JPS599927B2/en
Publication of JPS5533243A publication Critical patent/JPS5533243A/en
Publication of JPS599927B2 publication Critical patent/JPS599927B2/en
Expired legal-status Critical Current

Links

Abstract

PURPOSE: To prevent a fault from occurring in the execution of initial program loading, by providing a multiplexer channel with a circuit for AND operation between an IPL processing signal and device end signal.
CONSTITUTION: A multiplexer channel generates a select-out signal in order to secure a connection with an input-output device and in case of ordinary data transfer, it is disconnected from the input-output device by channel end signal CHE. Since, a connection to the input-output device is made again as soon as device signal DVE is generated, signal iPL and device end signal DVE are applied to AND circuit 22, shown in the figure, provided to the channel in an initial program loading (IPL) process and OR circuit 26 extracts a select-out reset signal, so that while the channel is not disconnected from the input-output device by signal CHE, it is disconnected by DVE.
COPYRIGHT: (C)1980,JPO&Japio
JP53106069A 1978-08-30 1978-08-30 Data transfer control method Expired JPS599927B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53106069A JPS599927B2 (en) 1978-08-30 1978-08-30 Data transfer control method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53106069A JPS599927B2 (en) 1978-08-30 1978-08-30 Data transfer control method

Publications (2)

Publication Number Publication Date
JPS5533243A true JPS5533243A (en) 1980-03-08
JPS599927B2 JPS599927B2 (en) 1984-03-06

Family

ID=14424302

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53106069A Expired JPS599927B2 (en) 1978-08-30 1978-08-30 Data transfer control method

Country Status (1)

Country Link
JP (1) JPS599927B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58186828A (en) * 1982-04-26 1983-10-31 Oki Electric Ind Co Ltd Protecting circuit of peripheral equipment
JPS59220819A (en) * 1983-05-30 1984-12-12 Fujitsu Ltd Resetting circuit

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3882757A1 (en) 2020-03-20 2021-09-22 Ricoh Company, Ltd. Display device, display method, and program

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58186828A (en) * 1982-04-26 1983-10-31 Oki Electric Ind Co Ltd Protecting circuit of peripheral equipment
JPS59220819A (en) * 1983-05-30 1984-12-12 Fujitsu Ltd Resetting circuit
JPH037983B2 (en) * 1983-05-30 1991-02-04 Fujitsu Ltd

Also Published As

Publication number Publication date
JPS599927B2 (en) 1984-03-06

Similar Documents

Publication Publication Date Title
JPS53112631A (en) Fault diagnosis device for computer system
JPS5580158A (en) False fault generation control system
JPS5533243A (en) Data transfer control system
JPS5391543A (en) Installation system for hdlc circuit
JPS53127248A (en) Composite computer system
JPS5416957A (en) Computer system for process control
JPS53149739A (en) Computer system
JPS5373934A (en) Data exchange control system
JPS55146559A (en) Data processing unit
JPS52107741A (en) Peripheral control unit
JPS559263A (en) System operation system
JPS5363829A (en) Generation control system of interrupt signal and interrupt circuit its execution
JPS5427756A (en) Discriminative switching system of troubled register
JPS5414647A (en) Signal processor
JPS5416955A (en) Computer system for process control
JPS52155924A (en) Data file control unit
JPS5343449A (en) Interruption system for electronic computer
JPS533144A (en) Operation procedure display unit
JPS5421229A (en) Data fetch system
JPS52142454A (en) Composite type processing device
JPS5697125A (en) Transmission control system for terminal controller
JPS53143367A (en) Electronic watch
JPS5539982A (en) Address control system of transmission address of local station
JPS53148240A (en) Parallel system between external memory and main memory
JPS53138240A (en) Data input control system