JPS5725042A - Microprocessor - Google Patents

Microprocessor

Info

Publication number
JPS5725042A
JPS5725042A JP10011380A JP10011380A JPS5725042A JP S5725042 A JPS5725042 A JP S5725042A JP 10011380 A JP10011380 A JP 10011380A JP 10011380 A JP10011380 A JP 10011380A JP S5725042 A JPS5725042 A JP S5725042A
Authority
JP
Japan
Prior art keywords
instruction
executing
time
executing time
microprocessor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10011380A
Other languages
Japanese (ja)
Inventor
Shinichi Tachikake
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP10011380A priority Critical patent/JPS5725042A/en
Publication of JPS5725042A publication Critical patent/JPS5725042A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)

Abstract

PURPOSE:To minimize a dead and idle time for processing, by providing an instruction executing time field consisting of information which is requird for deciding an executing time of the instruction, on an instruction and executed by a microprocessor. CONSTITUTION:An instruction kind discriminating field contained in an instruction word which has been outputted from a memory device 1 is decoded by a decoder 2a, its instruction is classified into kinds such as operation, transfer, etc., also an instruction executing time field contained in the instruction word is decoded by a decoder 2b, and length of an executing time of that instruction is classified. In accordance with outputs of the decoders 2a, 2b, a timing generating circuit 3 decides length of an executing time of the instruction, provides an instruction executing control pulse to an instruction executing circuit 4, and processsing indicated by the instruction word is executed. In this way, as for this microprocessor, its executing time is decided at every instruction, a dead and idle time is minimized, and a miximum processsing speed is displayed.
JP10011380A 1980-07-22 1980-07-22 Microprocessor Pending JPS5725042A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10011380A JPS5725042A (en) 1980-07-22 1980-07-22 Microprocessor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10011380A JPS5725042A (en) 1980-07-22 1980-07-22 Microprocessor

Publications (1)

Publication Number Publication Date
JPS5725042A true JPS5725042A (en) 1982-02-09

Family

ID=14265306

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10011380A Pending JPS5725042A (en) 1980-07-22 1980-07-22 Microprocessor

Country Status (1)

Country Link
JP (1) JPS5725042A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5925501A (en) * 1982-07-29 1984-02-09 Hitachi Ltd Controller for electric rolling stock
EP1518161A1 (en) * 2002-06-20 2005-03-30 Rambus Inc. Method and apparatus for the dynamic scheduling of device commands
US7565480B2 (en) 2002-06-20 2009-07-21 Rambus Inc. Dynamic memory supporting simultaneous refresh and data-access transactions

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5925501A (en) * 1982-07-29 1984-02-09 Hitachi Ltd Controller for electric rolling stock
EP1518161A1 (en) * 2002-06-20 2005-03-30 Rambus Inc. Method and apparatus for the dynamic scheduling of device commands
EP1518161A4 (en) * 2002-06-20 2007-02-21 Rambus Inc Method and apparatus for the dynamic scheduling of device commands
US7565480B2 (en) 2002-06-20 2009-07-21 Rambus Inc. Dynamic memory supporting simultaneous refresh and data-access transactions
US9824740B2 (en) 2002-06-20 2017-11-21 Rambus Inc. Dynamic memory supporting simultaneous refresh and data-access transactions
US10593390B2 (en) 2002-06-20 2020-03-17 Rambus Inc. Dynamic memory supporting simultaneous refresh and data-access transactions

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