JPS6435647A - Data processing system - Google Patents

Abstract

PURPOSE:To enable transfer between a memory and a CP through one bus cycle by adding a coprocessor space signal (CPS) and a coprocessor cycle signal (CPCYCL) or a command transfer cycle signal (AT2-0) to a coprocessor in addition to an ordinary memory access signal of a microprocessor. CONSTITUTION:When the microprocessor MPU1 fetches an instruction, which a coprocessor CP should process, it transmits an instruction CPS corresponding to this to the CP. At such a time, it transmits the AT2-0, showing that is is the bus cycle to transfer the instruction to the CP as well to the CP together with the instruction. In case of an operand is transferred from the memory 3 to the CP, the MPU1 asserts the signal CPYCL, showing the effectiveness of CP data in addition to the signal of ordinary memory read, and instructs the CP to fetch the data, and performs the transfer between the memory and the CP. In case of the data is transferred from the CP to the memory, the MPU asserts the CPCYCL signal, and instructs the CP to output the data to perform the transfer.