JPH03263128A - Microprocessor - Google Patents

Abstract

PURPOSE:To improve processing speed by deciding the status of a coprocessor in the bus control part of downstream of pipeline processing, and executing the next access instruction in accordance with the result of this decision. CONSTITUTION:In the case a busy instruction from a coprocessor 2 is received, a coprocessor deciding part 13B does not send out any information to a coprocessor deciding part 13A, and in the case the coprocessor 13A receives accessible instruction information OK from the coprocessor 2, a bus control part 13 executes immediately an access instruction to the coprocessor 2. That is, the accessible information OK is transferred to a bus control part 13 without allowing it to pass through an instruction control part 11 and an access control part 12. In such a way, the processing speed is increased by the two-stage portion of a pipeline.

Description

[Detailed Description of the Invention] [Summary] The present invention relates to a pipeline processing microprocessor in which a coprocessor dedicated to executing a special function is connected via a high-speed signal line, and an object of the present invention is to provide a microprocessor that improves processing speed. A microprocessor comprising an instruction control section, an access control section, and a bus control section arranged in a pipeline, and connectable to a coprocessor connected via a bus and a signal line, wherein the instruction control section and the bus control section are arranged in a pipeline. Each bus control unit is provided with a coprocessor determination unit that monitors the state of the coprocessor, and the coprocessor determination unit on the bus control unit side is configured to:
Among the response information from the coprocessor, information other than the busy instruction to wait for a report again is sent to the coprocessor determination unit on the instruction control unit side, and the coprocessor determination unit on the bus control unit side The bus control unit is configured to start accessing the coprocessor when the access permission instruction information is determined from the response information from the coprocessor.

[Industrial application field]

The present invention relates to a pipeline processing microprocessor in which a coprocessor dedicated to executing a special function is connected via a high-speed signal line.

[Prior art]

2. Description of the Related Art As semiconductor circuits have become more highly integrated in recent years, large-scale and highly functional microprocessors have been developed.

These microprocessors have functions comparable to those of large combi coaters. However, functions that require large-scale dedicated circuits, such as floating-point operations, are difficult to incorporate into a microprocessor due to the circuit scale.

Therefore, for functions that cannot be built into the microprocessor itself because they require large-scale circuits, a coprocessor dedicated to executing the above functions is manufactured separately, and this coprocessor and microprocessor are connected to a dedicated high-speed processor. By connecting the coprocessor with a signal line and activating the coprocessor according to instructions from the microprocessor when the above functions are required,
It is possible to make it appear as if the microprocessor itself has the above functions. Some microprocessors developed in recent years have such a signal line (coprocessor interface).

FIG. 6 is a circuit diagram showing a conventional processor system including a microprocessor and a coprocessor. In FIG. 6, the microprocessor 1 and the coprocessor 2 are connected to a bus 3 consisting of a control line CNT, an address line ADD, and a data line DT, and the state of the coprocessor 2 (coprocessor
It is connected by a high-speed dedicated signal line 4 for sending (status).

The microprocessor 1 employs pipeline processing,
It is composed of an instruction control section 11, an access control section 12, and a bus control section 13. In the coprocessor status signal S, information from the coprocessor 2 is sent to the microprocessor 1, and in the microprocessor 1, this information is judged by the coprocessor judgment unit 11A in the instruction control unit 11, and accordingly, the information is sent to the microprocessor 1. Determine the appropriate next action.

An example of coprocessor status information is shown in the table below.

The operation of the coprocessor instruction in the normal state shown in FIG. 6 will be explained with reference to FIG. That is, in cycle S0, the access instruction a of the coprocessor 2 is transferred to the access control section 12 by the signal S from the instruction control section 11, and in the next cycle S1, the access instruction a is transferred to the bus by the signal S2 from the access control section 12. Further to the control unit 13, the next cycle S2
In this case, the access instruction a is sent to the control line CNT by the signal S3 from the register 13A of the bus control unit 13, and in this case,
At the same time, address and data are also sent to address line ADD and data line DT (only data A on data line DT is shown).
is sent. As a result, when the coprocessor 2 is accessed and performs a predetermined process, it sends a process completion report OK (=010) to the coprocessor determination unit 11A of the instruction control unit 11 in cycle S3. In FIG. 6, the high-speed signal line 4 passes through the bus control section 13 and is connected to the command control section 11.
The data is directly supplied to the coprocessor determination unit 11A. As a result, in cycles S to S7, the same processing as above is performed regarding the access instruction.

Further, the coprocessor determination unit 11A determines whether other coprocessors or
When determining that status report has not arrived N0P=000, command error -011, etc., the command control unit 11 performs necessary reprocessing and the like.

[Problem to be solved by the invention]

However, as described above, there is a busy instruction (BUSY=001) that instructs to wait for a report again.

This is because if the coprocessor 2 takes a long time to process, and the microprocessor 1 is also stopped for a long time, it will not be able to accept urgent instructions such as interrupts. In some cases, coprocessor 2 temporarily returns the status so that it can be executed. When microprocessor 1 receives this instruction, it checks to see if there is an urgent instruction such as an interrupt. This is because if there is an instruction, the instruction is followed, and if there is no instruction, another part of the operation is to wait for the response OK=010 from the coprocessor 2.

That is, as shown in FIG. 8, when the coprocessor 2 generates a busy instruction (BUSY=001) as the coprocessor status in cycle S3, the next response is OK.
= Until (010), for example, cycle 84~
In S6, even if an urgent instruction such as an interrupt is not executed, the instruction control unit 11 cannot issue the next access instruction for the coprocessor 2, and the cycle S6
The instruction control unit 11 issues an access instruction for the first time in cycle S7 after the next response OK from the coprocessor 2 is received in step 6. Therefore, the accessible information is
For the bus control unit 13, the information is transmitted via the instruction control unit 11 and the access control unit 12, and pipeline processing is not utilized, and the processing of access instructions from the coprocessor 2 is delayed, which is not desirable in terms of processing speed. do not have.

Therefore, an object of the present invention is to provide a processor system with improved processing speed.

[Means to solve the problem]

A means for solving the above problem is shown in FIG.

That is, the microprocessor is equipped with an instruction control section 11, an access control section 12, and a right and bus control section 13 in a pipeline, and is connectable to a coprocessor 2 connected via a bus 3 and a high-speed signal line 4. , instruction control unit 11
Coprocessor determination units 11A and 13B are provided in the bus control unit and the bus control unit, respectively, for monitoring the status of the coprocessor 2. The coprocessor determination unit 11A on the bus control unit 11 side,
Among the response information S5 from the coprocessor, information S5+ other than the busy instruction BUSY, which instructs to wait for a report again, is sent to the coprocessor determination unit 11A on the instruction control unit side. Further, when the coprocessor determination unit 13B on the bus control unit 13 side determines that the access permission instruction information is OK from the response information S5 from the coprocessor 2 (SS), the bus control unit 13 starts accessing the coprocessor 2. Make it.

[For production]

According to the above-mentioned means, when there is a busy instruction from the coprocessor 2, the coprocessor determination unit 13B does not send any information to the coprocessor determination unit 13A, and the coprocessor determination unit 13B does not send any information to the coprocessor determination unit 13A, but only transmits the access permission instruction information from the coprocessor 2. When the coprocessor 13A receives the OK, the bus control unit 13 immediately issues an access instruction to the coprocessor 2. In other words, the access permission information OK is transmitted to the bus control section 13 without going through the instruction control section 11 and the access control section 12, and the processing speed is increased by two stages of the pipeline. Therefore, in this case, the instruction control unit 11A allows the instruction to access the coprocessor 2 to be issued twice in succession. In addition, in the instruction control unit 11, if only the transition to the next process is considered, if the coprocessor 2 returns a busy instruction, or if there is an interrupt, the next operation is canceled as in the case of an error. If there is no interrupt, if there is no interrupt, it is possible to pretend that the OK response has not been returned from the coprocessor 2, so that the instruction control unit 11 does not need to issue an access request again, and the next request can be processed. can be prepared, and pipeline processing can be effectively utilized.

〔Example〕

FIG. 2 is a plotted circuit diagram showing an embodiment of a processor system having a microprocessor according to the present invention, and is a circuit diagram in which a coprocessor determining section 13B is added to the circuit of FIG. 6. This coprocessor determination unit 13B sends all information other than the busy instruction BUSY (=001) among the coprocessor statuses from the coprocessor 2 to the coprocessor 11A of the instruction control unit 11, and also When it is determined that the instruction is possible (= 101), the bus control unit 13 registers the internal register 13A.
access to the coprocessor 2 immediately.

For this reason, the coprocessor determination section 13B is configured as shown in FIG.

In FIG. 3, information from the coprocessor 2 is temporarily stored in a register 131. This information is compared by a comparator 132 with the value 0.01 (representing BUSY) in a register 133, so that if the information is 001, the gate 134 is turned off, and if the information is other than 001, the gate 134 is turned off. The information is sent to the coprocessor determination unit 11 via the gate 134.
Sent to A. That is, information other than the busy instruction BUSY is sent to the coprocessor determination unit 11A.

Further, the information in the register 131 is compared with the value 101 (=OK) in the register 136 by the comparator 135, and as a result, if the information is 101, the internal register 13A
An access instruction signal a is sent to.

The operation of the coprocessor instruction in the normal state of FIG. 2 will be explained with reference to FIG. That is, in cycle S0, the access instruction a of the coprocessor 2 is sent to the access control unit 12 by the signal S1 from the instruction control unit 11, and in cycle S1
An access instruction a is sent to the bus control section by the output S2 from the access control section 12, and at the same time, an access instruction for the coprocessor 2 is sent to the access control section 12 by the signal S1 from the instruction control section. Furthermore, in the next cycle S2, the access instruction a is transferred to the control line CNT by the signal S3 from the register 13A of the signal S2 from the access control unit 12, and in this case, at the same time, the address line A
Address and data (A
(representatively shown) are sent out. As a result, when the coprocessor 2 is accessed and performs a predetermined process, such as a floating point operation, the process completion report is OK (=
101) is sent to the coprocessor determination unit 13B as a coprocessor status, and this coprocessor status OK is sent to the coprocessor 11A of the instruction control unit 11 in cycle S, and the instruction control unit 11 selects the next coprocessor. 2 access instructions become possible (note that this access instruction is not performed in FIG. 4). At the same time, in cycle S, the bus control unit 13 receives the determination result of the coprocessor status OK from the coprocessor determination unit 13B, and instructs access by the internal register 13A. It is sent to address line ADD and data line DT. As a result, when the coprocessor 2 is accessed and performs a predetermined process, a process completion report OK is sent to the coprocessor determination unit 13B in cycle S, and then a process completion report OK is sent in cycle S6.
will be sent to the coprocessor determination unit 11A.

In this way, the instruction control unit 1 utilizes pipeline processing.
1 can successively generate access instructions a and b.

The operation of the coprocessor instruction in the case of the busy instruction shown in FIG. 2 will be explained with reference to FIG.

The process up to cycle S2 is the same as that shown in FIG.

When the coprocessor 2 generates a busy instruction BUSY as the coprocessor status in cycle S3, even if it reaches the coprocessor determination section 13B (S,), it does not reach the coprocessor determination section 11A (SS'). therefore,
In the instruction control unit 11, the bus control unit 13 waits for an OK response from the next coprocessor, and the instruction control unit 11 and access control unit 12 remain in the same state as when no response has been received.

During this period, the instruction control unit 11 executes any urgent instruction such as an interrupt, as described above.

Then, in cycle S7, the bus control unit 13 issues an access instruction using the signal S3 from the internal register 13A to the control line CNT, and in this case, the address and data B are simultaneously sent to the address line ADD and the data line DT. , As a result, the coprocessor 2 executes the access instruction.

Thus, in FIG. 5, the processing for access instruction b (cycle S7) is faster than the processing for access instruction b (cycles 87 to Ss) in the conventional FIG.

〔Effect of the invention〕

As explained above, according to the present invention, the status of the coprocessor is determined in the bus control unit downstream of the pipeline processing, and the next access instruction is issued according to the result of this determination, so that the pipeline processing can be effectively utilized. It is possible,
Processing speed can be improved.

[Brief explanation of drawings]

FIG. 1 is a block circuit diagram including the basic configuration of a microprocessor according to the present invention, FIG. 2 is a block circuit diagram showing an embodiment of a processor system having a microprocessor according to the present invention, and FIG. 4 and 5 are timing diagrams explaining the circuit operation of FIG. 2. FIG. 6 is a block circuit diagram showing a processor system having a conventional microprocessor. , Figures 7 and 8 are the 6th
FIG. 3 is a timing diagram illustrating the operation of the circuit shown in the figure. 1: Microprocessor, 2: Coprocessor, 1
1: Instruction control unit, 12: Access control unit, 13
: bus control unit, 11A, 13B: coprocessor determination unit.

Claims (1)

[Claims] 1. An instruction control section (11), an access control section (12), and a bus control section (13) are arranged in a pipeline, and a command control section (11), an access control section (12), and a bus control section (13) are provided, and the Processor (2)
A microprocessor connectable to a microprocessor, wherein the instruction control unit and the bus control unit each include a coprocessor determination unit (
11A, 13A), and the coprocessor determining unit on the bus control unit side passes information (S_S') other than the busy instruction that instructs to wait for a report again from the response information (S_S) from the coprocessor to the command. When the coprocessor determining unit on the bus controller side determines access permission instruction information from the response information from the coprocessor, the bus controller determines whether the bus controller accesses the coprocessor. microprocessor to start.