JPS6352241A - Microprocessor - Google Patents

Abstract

PURPOSE:To process data at a high speed via a context switching or return action by providing a pointer which designates register groups and a circuit which detects the overflow of the pointer. CONSTITUTION:An MPU contains register groups A-N obtained by dividing the inside area of a RAM and a condition register CR which detects the overflow. These register groups A-N include program counters PCA-N, stack pointers SPA-N, various registers REA-N, and pointers A-N respectively. When an interruption signal is delivered from an interruption circuit INT, the CR gives an indication to an instruction decoder DCR to give accesses to the register groups in the order of A and B-N. When a context switching action occurs in an application mode of the final group N, the CR detects an overflow and produces an interruption signal to deliver the control to a central processing unit.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microprocessor, and relates to a technique that is effective for use in, for example, a microprocessor having a plurality of register groups.

[Conventional technology]

When a context switch occurs due to a subroutine call or task switch, the microprocessor saves the contents of various registers used to execute the current program, or conversely, uses the contents of the saved registers as the base. This data processing is performed by restoring the data into the registers of the memory, which is performed using the stack (memory) and the stack pointer. The saving/recovery of such a register group is described, for example, in CQ Publishing, September 15, 1988, Microcomputer Internal Structure and Machine Language, written by Kunio Fukunaga, pp. 163-196. .

[Problem that the invention seeks to solve]

When executing a program in which the above-mentioned context switches occur frequently, time is spent saving and restoring the contents of the various registers, which slows down the actual data processing speed.

An object of the present invention is to provide a microprocessor that improves data processing speed with context switching.

The above and other features and novel features of the present invention will become apparent from the description and accompanying drawings.

[Means for solving problems]

A brief overview of typical inventions disclosed in this application is as follows.

In other words, multiple sets of registers are provided and this management is performed in one register group.
This is done using a pointer that specifies one register group and a detection circuit that detects overflow of the pointer.

[For production]

According to the above means, the register group is switched every time a context switch occurs, and when the number of context switches exceeds the number of register groups, the context switch is performed by performing a predetermined process according to the detection signal. Data processing associated with returns and returns can be performed at high speed.

〔Example〕

FIG. 1 shows a block diagram of an embodiment of a microprocessor according to the present invention. Each circuit block constituting the microprocessor MPU (LSI) surrounded by dotted lines in the figure is formed on a single semiconductor substrate such as single crystal silicon using known semiconductor integrated circuit manufacturing techniques, although not particularly limited thereto. be done.

In this embodiment, in order to enable data processing with high-speed context switching, a plurality of register groups consisting of A to N are provided, although not particularly limited thereto. Each of these register groups A-N is divided and configured within an area of a built-in RAM. The above register groups A to N are program counters PCA to PAN, stack pointers SPA to SPN, and various registers REA to R, respectively, which are necessary for executing instructions of a predetermined program.
They each consist of EN and pointers A to N.

Each of these register groups is connected to three internal buses B1 to B3.
It is connected to each of the following circuit units by a bus.

The arithmetic and logic unit (ALU) receives data from the bus B1 and a signal from a launch (achiemulator) FF that takes in the data supplied via the bus B1, and performs control formed by decoding a command word. Arithmetic or logical operation is performed according to the signal, and the result of this operation is transferred to bus B2.
is output to and taken into each of the above register groups.

Further, a data buffer DB is provided for exchanging data with an external memory and the like. Data is transferred between the data buffer DB and the bus B1 and the bidirectional data buffer DAB, although this is not particularly limited. That is,
Data on the external data bus read from an external memory or the like is taken in by the bidirectional data buffer DAB.

The signal D1 of this bidirectional data buffer DAB is sent to the internal bus B1 via the data buffer DB.

Conversely, data on the internal bus Bl that is generated by the arithmetic operation unit (ALU) and to be sent to an external memory device or the like is taken into the data buffer DB. And the bidirectional data buffer DAB
is sent out on the external bus via On the other hand, address No. 18 on bus B1 is sent to the external bus via address buffer AB and address output circuit ADB.

This allows access to external memory devices and input/output devices.

Further, the command words of the program stored in the external memory device are taken into the bidirectional data buffer DAB. This instruction word is sent to the instruction register IR. The instruction word taken into the instruction register IR is supplied to a microprogram ROM (hereinafter simply referred to as mROM).

This mROM is used to read microinstructions consisting of a plurality of steps according to the instruction word.

This microinstruction is fed on the one hand to the decoder DCR, which transfers the data via the internal bus,
Operation of various registers and arithmetic logic operation unit 7) ALU
generates various control signals and timing signals necessary for the operation of the Furthermore, the microinstructions mentioned above are fed back to the input side on the other hand and are used for conditional jumps and next address designation. In this way, a macroinstruction supplied from an external memory or the like is executed by a microinstruction consisting of multiple steps stored in the mROM.

Also, when the interrupt circuit INT receives the interrupt,
Access condition register CR. The condition register CR corresponds to the pointers of the register groups A to N and instructs the execution of instructions according to their states.

When there is an interrupt from the interrupt circuit INT, the condesion register CR causes the instruction decoder DC to access the vacant register group from the pointer.
Instruct R. Further, the instruction decoder DCR accesses a group of free registers from the above pointer in response to a subroutine call.

After the system is reset, all the register groups are empty, so for example, register group A is used to execute a predetermined program. Of each register group A to N,
The pointer for register group A is currently in use, and the pointers for register groups B through N are empty.

In this state, when context switches occur one after another, in other words, the register groups are switched and used in the order of B, CN as the subprogram calls become more multiplexed. Conversely, as the multiplicity becomes shallower upon return from the subprogram, switching in the opposite direction is performed, such as NC, B, and A. When this switching occurs, each program is interrupted, but the data at each interruption is retained by the program counter and registers, so there is no need to save the data. will be held.

If a context switch occurs while using the final register group N, the condesion register CR detects an overflow.

The processing when this overflow occurs is (1
) For example, when generating an interrupt signal and passing control to the central processing unit, (2) Setting a flag indicating that an overflow has occurred, executing the program using the first register group A, and returning to the previous program. It is possible to check that the contents have been destroyed. (3
) Various types of processing become possible, such as by saving the necessary data in the register group to create an empty register group, and then executing the instructions continuously.

The effects obtained from the above examples are as follows. In other words, (11) By providing multiple sets of register groups and managing them using a pointer that specifies one register group and a detection circuit that detects overflow of the pointer, the register group is managed every time a context switch occurs. When a context switch occurs and the number of register groups exceeds the number of register groups, predetermined processing is performed in accordance with the detection signal, thereby achieving the effect that arithmetic evaluation and subprogram call return can be performed efficiently.

(2) By configuring the register group using a built-in RAM, it is possible to mount a large number of register groups on a semiconductor substrate with high density.

(3) According to (1) above, if there is a vacant register group among a plurality of register groups, it is possible to use the register group without checking the stack or the register group for overflow every time.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Also. For example, a direct memory access control circuit may be built into the microprocessor to automatically save the register group based on the overflow detection signal. In this case, all register groups may be saved. Once data is stored, data can be automatically saved and restored for that one register group. In addition, the above register group is the built-in RAP
In addition to being configured using vl, they may be configured using independent circuits. Furthermore, the register group switching system j1 method described above can be implemented in various embodiments.

Furthermore, the number and arrangement of internal buses that connect the plurality of register groups to the arithmetic and logic operations, each buffer, etc. can take various embodiments.

This invention can be widely used in microprocessors.

〔Effect of the invention〕

By providing a plurality of register groups and performing this management using a pointer that specifies one register group and a detection circuit that detects overflow of the pointer, the register group is switched every time a context switch occurs. When a context switch occurs exceeding the number of register groups, arithmetic evaluation and subprogram call recovery can be performed efficiently by performing predetermined processing according to the detection signal.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

Claims (1)

[Scope of Claims] 1. Includes a plurality of register groups required for instruction execution, a pointer for specifying a register group used for program execution, and a detection circuit for detecting overflow of the pointer. Features a microprocessor. 2. The microprocessor according to claim 1, wherein the plurality of register groups are configured by built-in RAM.