JPS6462701A - Programmable controller - Google Patents

Programmable controller

Info

Publication number
JPS6462701A
JPS6462701A JP62220010A JP22001087A JPS6462701A JP S6462701 A JPS6462701 A JP S6462701A JP 62220010 A JP62220010 A JP 62220010A JP 22001087 A JP22001087 A JP 22001087A JP S6462701 A JPS6462701 A JP S6462701A
Authority
JP
Japan
Prior art keywords
coil
logical
instruction
ladder
processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62220010A
Other languages
Japanese (ja)
Inventor
Mikio Yonekura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fanuc Corp
Original Assignee
Fanuc Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fanuc Corp filed Critical Fanuc Corp
Priority to JP62220010A priority Critical patent/JPS6462701A/en
Publication of JPS6462701A publication Critical patent/JPS6462701A/en
Pending legal-status Critical Current

Links

Landscapes

  • Executing Machine-Instructions (AREA)
  • Programmable Controllers (AREA)

Abstract

PURPOSE:To execute the processing at a high speed by writing a value to a coil, when a logical condition of its coil has been determined by a logical condition of a ladder diaphragm, and executing an arithmetic operation of the next coil. CONSTITUTION:An arithmetic processor 10 executes successively a logical instruction of a ladder diaphragm which has been stored in an instruction memory 1, and reads out a bit data designated from a data memory 2, namely, a designated contact. Subsequently, its data is stored in a bit register 18, and the next instruction is executed by its logical state, or when a value of a coil of its ladder diaphragm has been determined, its value is written in a bit of a coil of the data memory 2, and an offset of a jump destination is added to a program counter 16, and allowed to jump. In such a way, by kind of the instruction and a result of logical operation, an unnecessary logical operation is omitted, and immediately, the processing jumps to a logical processing instruction of the next coil, therefore, the sequence processing of the ladder diagram can be executed at a high speed.
JP62220010A 1987-09-02 1987-09-02 Programmable controller Pending JPS6462701A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62220010A JPS6462701A (en) 1987-09-02 1987-09-02 Programmable controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62220010A JPS6462701A (en) 1987-09-02 1987-09-02 Programmable controller

Publications (1)

Publication Number Publication Date
JPS6462701A true JPS6462701A (en) 1989-03-09

Family

ID=16744515

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62220010A Pending JPS6462701A (en) 1987-09-02 1987-09-02 Programmable controller

Country Status (1)

Country Link
JP (1) JPS6462701A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002099311A (en) * 2000-09-25 2002-04-05 Yaskawa Electric Corp Method for preparing motion program and motion controller

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002099311A (en) * 2000-09-25 2002-04-05 Yaskawa Electric Corp Method for preparing motion program and motion controller

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