JPS57108935A - Program memory control system - Google Patents

Program memory control system

Info

Publication number
JPS57108935A
JPS57108935A JP18880780A JP18880780A JPS57108935A JP S57108935 A JPS57108935 A JP S57108935A JP 18880780 A JP18880780 A JP 18880780A JP 18880780 A JP18880780 A JP 18880780A JP S57108935 A JPS57108935 A JP S57108935A
Authority
JP
Japan
Prior art keywords
rom
instruction
outputted
incorporated
switching signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18880780A
Other languages
Japanese (ja)
Inventor
Shozo Shirota
Masaaki Ueno
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP18880780A priority Critical patent/JPS57108935A/en
Publication of JPS57108935A publication Critical patent/JPS57108935A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/22—Microcontrol or microprogram arrangements
    • G06F9/223—Execution means for microinstructions irrespective of the microinstruction function, e.g. decoding of microinstructions and nanoinstructions; timing of microinstructions; programmable logic arrays; delays and fan-out problems

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)

Abstract

PURPOSE:To flexibily use an internal and an incorporated ROM for proper purposes, by addressing the external ROM having the same capacity with the incorporated ROM without increasing the number of bits of a program counter. CONSTITUTION:On the basis of a flag output 18 outputted from an ROM selection flag 17, an incorporated ROM2 or an external ROM6 is selected. An ROM switching signal 16 is outputted accompanying a specific instruction like a jump instruction. If this instruction is executed while an ROM1 undergoes execution, it is decoded by an instruction decoder 15, and then the ROM switching signal 16 is outputted. The ROM selection flag 17 changes in contents in response to the input of the ROM switching signal 16, and at the same time a jump is also made.
JP18880780A 1980-12-25 1980-12-25 Program memory control system Pending JPS57108935A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18880780A JPS57108935A (en) 1980-12-25 1980-12-25 Program memory control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18880780A JPS57108935A (en) 1980-12-25 1980-12-25 Program memory control system

Publications (1)

Publication Number Publication Date
JPS57108935A true JPS57108935A (en) 1982-07-07

Family

ID=16230141

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18880780A Pending JPS57108935A (en) 1980-12-25 1980-12-25 Program memory control system

Country Status (1)

Country Link
JP (1) JPS57108935A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5986100A (en) * 1982-11-09 1984-05-18 三洋電機株式会社 Voice synthesizer
JPS6033645A (en) * 1983-08-05 1985-02-21 Nec Ic Microcomput Syst Ltd Memory switching device
JPS6051957A (en) * 1983-08-31 1985-03-23 Toshiba Corp Microprocessor system
JPS6086636A (en) * 1983-10-18 1985-05-16 Nec Corp Information processing device with address switching circuit

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5986100A (en) * 1982-11-09 1984-05-18 三洋電機株式会社 Voice synthesizer
JPH0372988B2 (en) * 1982-11-09 1991-11-20 Sanyo Electric Co
JPS6033645A (en) * 1983-08-05 1985-02-21 Nec Ic Microcomput Syst Ltd Memory switching device
JPS6051957A (en) * 1983-08-31 1985-03-23 Toshiba Corp Microprocessor system
JPH027097B2 (en) * 1983-08-31 1990-02-15 Tokyo Shibaura Electric Co
JPS6086636A (en) * 1983-10-18 1985-05-16 Nec Corp Information processing device with address switching circuit
JPH0221620B2 (en) * 1983-10-18 1990-05-15 Nippon Electric Co

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