JPS5776637A - Microprocessor on microprogram control system - Google Patents

Microprocessor on microprogram control system

Info

Publication number
JPS5776637A
JPS5776637A JP15343380A JP15343380A JPS5776637A JP S5776637 A JPS5776637 A JP S5776637A JP 15343380 A JP15343380 A JP 15343380A JP 15343380 A JP15343380 A JP 15343380A JP S5776637 A JPS5776637 A JP S5776637A
Authority
JP
Japan
Prior art keywords
address
rom1
selector
read out
information
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15343380A
Other languages
Japanese (ja)
Other versions
JPS6138495B2 (en
Inventor
Shigeaki Hirano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP15343380A priority Critical patent/JPS5776637A/en
Publication of JPS5776637A publication Critical patent/JPS5776637A/en
Publication of JPS6138495B2 publication Critical patent/JPS6138495B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/22—Means for limiting or controlling the pin/gate ratio

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microcomputers (AREA)

Abstract

PURPOSE:To execute an external microprogram without requiring so many pins of a chip, by utilizing an address bus. CONSTITUTION:When the address of a microinstruction indicates an ROM1, an address selector 3 supplies an address which indicates a field NA to the ROM1, from which microinstructions in its chip are read out. An NA selector 4 selects the information read out of the ROM1, set it in a register 2, and executes it. When the address of the microinstruction indicates an external storage device, on the other hand, the address information of a next microinstruction is outputted onto an address bus 6 through a gate 5. A microinstruction read out of the external storage device is set in a register 8 from the address bus 6 through a gate 7, and an address information on a field ROMA is supplied to the ROM1 through the selector 3. Further, NA field information is sent to the NA selector 4 to select the information read out of the ROM1, and the instruction is executed.
JP15343380A 1980-10-31 1980-10-31 Microprocessor on microprogram control system Granted JPS5776637A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15343380A JPS5776637A (en) 1980-10-31 1980-10-31 Microprocessor on microprogram control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15343380A JPS5776637A (en) 1980-10-31 1980-10-31 Microprocessor on microprogram control system

Publications (2)

Publication Number Publication Date
JPS5776637A true JPS5776637A (en) 1982-05-13
JPS6138495B2 JPS6138495B2 (en) 1986-08-29

Family

ID=15562404

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15343380A Granted JPS5776637A (en) 1980-10-31 1980-10-31 Microprocessor on microprogram control system

Country Status (1)

Country Link
JP (1) JPS5776637A (en)

Also Published As

Publication number Publication date
JPS6138495B2 (en) 1986-08-29

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