JPS6448164A - Processing end interrupt control system - Google Patents

Processing end interrupt control system

Info

Publication number
JPS6448164A
JPS6448164A JP20546087A JP20546087A JPS6448164A JP S6448164 A JPS6448164 A JP S6448164A JP 20546087 A JP20546087 A JP 20546087A JP 20546087 A JP20546087 A JP 20546087A JP S6448164 A JPS6448164 A JP S6448164A
Authority
JP
Japan
Prior art keywords
processing
execution
control information
command word
interrupt
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP20546087A
Other languages
Japanese (ja)
Other versions
JPH07111711B2 (en
Inventor
Katsuichi Hirowatari
Kunihiro Ohata
Osamu Suzuki
Shigeyuki Morioka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP20546087A priority Critical patent/JPH07111711B2/en
Publication of JPS6448164A publication Critical patent/JPS6448164A/en
Publication of JPH07111711B2 publication Critical patent/JPH07111711B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PURPOSE:To easily transfer data in the distributed processing or the like by storing report destination information, which reports the end of the processing by an interrupt after the end of the processing, in a command word. CONSTITUTION:A command word 1 is provided where control information required for execution of devices 3-1-3-4 using memories 5-1 and 5-2 as shared resources and interrupt control information related to a system to which the end of this execution should be reported at the time of the end of execution are stored. Some system stores prescribed control information in this command word and requests the processing to devices 4-1 and 4-2 used as shared resources, and these devices report the end of the processing to the pertinent system by an interrupt based on interrupt control information stored in this command word after terminating the processing. Thus, the execution result can be reported to any system after execution of the command to shared resources.
JP20546087A 1987-08-19 1987-08-19 Processing end interrupt control system Expired - Fee Related JPH07111711B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20546087A JPH07111711B2 (en) 1987-08-19 1987-08-19 Processing end interrupt control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20546087A JPH07111711B2 (en) 1987-08-19 1987-08-19 Processing end interrupt control system

Publications (2)

Publication Number Publication Date
JPS6448164A true JPS6448164A (en) 1989-02-22
JPH07111711B2 JPH07111711B2 (en) 1995-11-29

Family

ID=16507243

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20546087A Expired - Fee Related JPH07111711B2 (en) 1987-08-19 1987-08-19 Processing end interrupt control system

Country Status (1)

Country Link
JP (1) JPH07111711B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04123234A (en) * 1990-09-14 1992-04-23 Hitachi Ltd Process scheduling system and memory control system for multiprocessor
JP2013025590A (en) * 2011-07-21 2013-02-04 Hitachi Ulsi Systems Co Ltd Arithmetic processing unit and microcomputer

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04123234A (en) * 1990-09-14 1992-04-23 Hitachi Ltd Process scheduling system and memory control system for multiprocessor
JP2013025590A (en) * 2011-07-21 2013-02-04 Hitachi Ulsi Systems Co Ltd Arithmetic processing unit and microcomputer

Also Published As

Publication number Publication date
JPH07111711B2 (en) 1995-11-29

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Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees