JPH04123234A - Process scheduling system and memory control system for multiprocessor - Google Patents

Abstract

PURPOSE:To improve the access speed of a processor by allowing a process scheduler to allocate respective processors to respective processes in accordance with the output of a determining means for calculating a candidate process to be executed by using process allocation information stored in a process allocation information storing means. CONSTITUTION:A process control table 50 is provided with plural process allocation information storing means 52 to 56 for storing a list of a main memory 23 having programs or data for operating respective processes and the determining means 57 for calculating a candidate process to be executed next by using the process allocation information and the process scheduler allocates a processor to the calculated process in accordance with the output of the means 57. Thereby, CPUs 20A, 20B having the most programs or data relating to the processes can be allocated to the processes. Consequently, an average memory access time can be shortened and a practical processor access speed can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to process scheduling of a shared memory type multiprocessor provided in a CPU (Central Processing Unit), and in particular to distributed arrangement of shared memory near each processor. The present invention also relates to a multiprocessor process scheduling method and memory management method suitable for improving the performance of the entire system.

[Conventional technology]

In conventional multiprocessor process scheduling methods, as the computing power required of computers continues to increase, multiprocessor methods are known in which parallel processing is performed by a plurality of processors. Among these, a shared memory type multiprocessor in which multiple processors share one memory is said to be highly versatile.

In general, shared memory multiprocessors are processors,
A shared memory, an I10 device, etc. are connected via one shared bus, and each processor accesses the memory via the shared bus. For this reason, it is known that the shared bus tends to become an overall bottleneck. So usually,
Each processor is provided with a cache memory to reduce access to the shared bus.

This cache memory not only reduces access to the shared bus but also reduces the average memory access time, so it is an important element that affects system performance. Therefore, in order to make effective use of this cache memory,
Inventions such as Japanese Patent No. 2-115567 have been made.

However, cache memory is originally a small capacity, high speed memory, and does not guarantee that it will be possible to reduce common bus accesses or fundamentally shorten memory access time. In particular, as the operating frequency of processors increases and performance increases, the penalty at cache hit becomes a problem. That is, the difference in memory access time between a cache hit and a miss increases, and if the miss rate increases even a little, the average memory access time will deteriorate significantly.

The solution to this problem is a multiprocessor with local memory (distributed main memory). Generally, local memory is placed near the processor, for example on the same printed board, so the electrical delay time when accessing the local memory is small1, and since a shared bus is not used, high-speed memory access can be ensured. One of the drawbacks of this method is that when access to other local memories occurs, the access time becomes longer. This can be understood to be exactly the same situation as a normal multiprocessor that accesses shared memory via a shared bus. Japanese Patent Application Laid-Open No. 62-115567 describes improvements to software for increasing the cache memory hit rate, but does not discuss a method for concentrating access to the local memory of its own processor in a multiprocessor with local memory. It wasn't taken into account.

[Problem to be solved by the invention]

In conventional multiprocessor process scheduling methods, even if cache memory is used, the miss rate increases and memory access time deteriorates, access time to other local memory becomes longer, or the self-processor There were problems such as no consideration was given to a method for concentrating access to local memory.

An object of the present invention is to provide a process scheduling method and a memory management method for a multiprocessor in which programs are arranged so that each processor having a distributed main memory stores programs or data to be executed within the distributed main memory as much as possible. Our goal is to provide the following.

Another object of the present invention is to provide a scheduler having an interface that can request a system to store programs or data to be executed by each processor in distributed main memories as much as possible.

Another object of the present invention is to detect when the main memory of another processor is accessed, and to extract a certain amount of memory from the main memory of the other processor.

An object of the present invention is to provide a memory management method that performs bulk transfer to the main memory of its own processor and prevents access to the main memory of other processors via a shared bus thereafter.

[Means to solve the problem]

In order to achieve the above object, a multiprocessor process scheduling method according to the present invention includes a plurality of CPUs each consisting of a plurality of processors and a main memory shared by each processor, and each processor has an internal memory. A multiprocessor process in which each processor can freely access each other's memory via a communication path connecting the processor and other processors, and a process scheduler assigns any processor to a process in an executable state according to a process management table. In the scheduling method, the process management table includes a process allocation information storage means that stores a list of main memory containing programs or data for operating each process, and a process allocation information that calculates a candidate process to be executed next. and determining means, and the process scheduler allocates processors to processes according to the output of the determining means.

The process allocation information storage means is for each C
The configuration is such that the number of pages mapped to the main memory within the PU and used for each process is stored for each CPU.

Further, the determining means is the C in which the process scheduler is operating.
This configuration calculates executable processes whose programs or data are all held in the main memory within the PU as candidates.

Furthermore, the determining means may be configured such that the process scheduler calculates as a candidate an executable process in which the largest number of programs or data are held in the main memory of the CPU in operation.

It is equipped with a plurality of CPUs consisting of a plurality of processors and a main memory shared by each processor. In a multiprocessor process scheduling method in which mutual memory is freely accessible and a process scheduler assigns any processor to a process in an executable state according to a process management table, the process management table specifies in advance the processor to be assigned to each process. The present invention may be configured to include a process allocation information storage means and a determining means for calculating a candidate process to be executed next using the process allocation information, and a process scheduler allocates a processor to a process according to the output of the determining means.

Further, the process allocation information storage means is configured to hold identifiers of processors allocated to each process.

Further, the determining means calculates as candidates an executable process for which the process scheduler specifies a running processor.The determining means calculates as a candidate an executable process for which the process scheduler specifies a running processor. A configuration may also be used.

It is equipped with a plurality of CPUs consisting of a plurality of processors and a main memory shared by each processor, and each CPU can communicate with each other via a communication path connecting the internal processor and other processors. In a memory management system for a multiprocessor that allows access to the memory of another CPU, an external access detection means detects that the main memory of another CPU is accessed and notifies the processor of the CPU that has generated the access, and an external access detection means a communication means for communicating the output of the to the operating system;
and page transfer means for transferring the page of the access target area to the main memory within its own CPU in accordance with the output of the transfer means.

The external access detection means is configured not to detect external access while the page transfer means is operating.

Further, the page transfer means is configured to issue a request to invalidate the access target area to the CPU that has the page of the access target area, and the CPU drops the valid flag of the access target area in accordance with the request.

Furthermore, the transmission means is configured to operate only when the transmission permission flag of the page management table of the access target area is valid.

[Effect]

According to the multiprocessor process scheduling method of the present invention, each page, which is the smallest unit of memory management, is given an identifier indicating which processor's memory it belongs to, so that the scheduler that schedules processes can interpret this. Then, the processor that has all or the most pages for the next process to be executed is assigned to this process.

Then, when accessing memory, a means is provided to detect whether or not this access is to the memory in the own processor, so if the access is to the memory in another processor,
The processor is notified as a bus error. Then, the processor performs processing similar to a so-called page fault, transfers the page in the memory in the other processor to a free page in the memory in its own processor, and resumes memory access.

〔Example〕

An embodiment of the present invention will be described with reference to FIG.

As shown in FIG. 1, a CPU (central processing unit) 20 has a plurality of processors 21 and a main memory (distributed main memory) 23 shared by each of the processors 21. If current mounting technology is used, it can be mounted on a single standard printed circuit board, and the processor 21
can realize a virtual memory such as Motorola's MC68020. Memory management unit i (MMU) 2
2 is an address translation table that divides the virtual memory space and the physical memory space into page units (4 KB in this example), maintains the correspondence between them, and is stored in the LMS 23 (distributed main memory). Manage. and,
The virtual address output from the processor 21 is converted into a physical address according to the address conversion table, and the cache memory is first searched. Further, if write protection or other protection is applied to the page, this is checked during address conversion, and when a protection error occurs, it is notified to the processor 21 via the signal line 25 as a bus error. LMS23 is CPU2
It is shared by the processor 21 in the OA via the signal line 26, and shared by the external CPU 2OB via the bus signal line 28 and the bus interface device 24. The bus signal line 28 may be a conventional metal wire or an optical fiber. The signal line 27 (communication path) 27 is C
This is a signal line for communication between PU2OA and PU2OB, and by accessing a specific address (not shown) mapped in the memory space of the processor, the signal line 27 output from the own CPU is turned on. It can be done. When the signal line 27 to the CPU itself is turned on, it is converted into an interrupt signal 27A to the processor by the bus interface 24, and the processor 21 is notified. In this embodiment, the signal line 27 is set for each CPU, but in order to reduce the number of signal lines,
It is also possible to make it into a curved shape.

The difference between the main memory (GMS) 29 shared by all CPUs and the LMS 23 is that the access times seen from the processor are different. The access time from the processor 21 in one CPU2OA to the LMS 23 is the fastest, and the access time from any processor 21 to the 0MS 29 is the second fastest. And from other CPU2OB
The access time to MS23 is the slowest.

FIG. 2 shows the LMS area 31 in the physical memory space 3o.
This shows the mapping state of the 0MS area 32. This real memory is divided into 1 page of 4KB, and the serial number is 31A.
, 31B and manage it.

In this embodiment, consecutive physical addresses are assigned to each LMS area 31A and 31B, but considering that the LMS area will be expanded in the future, a physical memory space larger than the LMS to be implemented is secured in advance. It is also possible. In this case, if an unimplemented physical memory space is accessed, a memory access error will occur due to the MMU.

Figure 3 shows one of the address translation tables managed by the MMU.
It shows an entry and corresponds one-to-one with one page of physical memory. Valid bit
35 indicates that this entry holds a valid value when the value is 1, and the page number P F N (Page
3 G indicates the number of the page managed by this entry. M (Modi
fid bit) 37 indicates that a write has been made to this page when the value is 1. S (Superviso
rProtection) 38 indicates whether access only in supervisor mode (OA privilege mode) is permitted. A value of 1 indicates that the page can only be accessed by supervisors. Whether the supervisor has accessed or not can be determined by an output signal line from a processor (not shown). W(Write
Protection) 41 is a bit indicating write protection, and when writing is performed on a page in which one bit is 1, a write protection error is detected and notified to the processor as a bus error.

RC (Reference Control) 42
is a field that records the history of memory accesses to this page, and serves as a criterion when transferring a page from memory to secondary storage such as a disk device.

#MEM (Local Main Stora
ge Number) 43 (R brush) is a field indicating the number of the CPU where this page exists. The MMU 22 shown in FIG. 1 compares this field with the output of the CPU ID 120 that holds its own CPU number.
Is the access to the LMS within its own CPU or to another CPU?
It is determined whether the access is to the LMS of the PU, and if the access is to another CPU, a pseudo page fault is generated (described later) and the processor is notified as a bus error.

However, this fault is suppressed by the suppression bit I (Main S
storageAccessFaultInh-ib
it) In this example, it is possible to suppress by 44:
Since the number of CPUs is 4, #MEM43 only needs to be 3 bits, of which 00 to 100 are made to correspond to each CPU, and 111 is used to specifically indicate GMS. L
(Page 1.ock) 45 indicates whether access to the page is locked. When a page is locked, access to that page is suspended until the page is unlocked.

FIG. 4 is a detailed configuration diagram of a bus error detection circuit included in the MMU. AND gate 123°OR gate 124
External access detection means consisting of a FOR (exclusive OR) gate 125 and an inverter 126 are shown. The access identification signal 121 is a read/write signal output from the processor, and shows a CPU number 120 and values 39 to 45 obtained from each field of the selected page table entry. Signal line 12
A signal line 2 conveys bus errors caused by other factors such as parity errors, address overflows, and page faults. This detection circuit operates every time the processor requests external memory access and the MMU performs address translation. When an error is detected, the bus error signal transmission means 25 is turned on to notify the processor, and an error factor flag (not shown) is turned on.

Figure 5 shows the bus error detection circuit, and shows various bus error detection circuits.
3 is a flowchart showing software error processing after detection of the error. The factor determination parts 131 to 134 are
The determination is completed by searching for the factor flag. In the case of an illegal write access, the write protect error processing 135 performs processing to interrupt the process that caused the access, or in the case of a copy-on-write method, creates a new page (copy )I do.

Read protection error processing 137 is illustrated.

Although the detailed processing flow is not described in this example, if the copy-on-write method is adopted and the child process is executed on a CPU different from the CPU on which the parent process is executed, the child A read protection error occurs when a process performs read access. Then, from the LMS of the CPU where the parent process is being executed within this process,
Forward (copy) the page containing the address that caused the lead protection error.

FIG. 6 shows a detailed flow of the pseudo page fault processing 136 that occurs when an LMS other than the own CPU is accessed. It is determined whether or not there is a free page in the LMS within the own CPU (140). If it exists, the page (transfer page) containing the pseudo page fault address is locked, that is, the L bit of the page table entry 40 of that page is turned on (141). Then, using the communication line 27 shown in FIG. 1 between the processors, the TLB (address translation buffer) containing the page table entry is invalidated and the cache memory holding the data of the transferred page is invalidated for all processors. (142). Thereafter, the transfer page is transferred to the LMS within the own CPU (143), and the contents of the page table entry 40 corresponding to the transfer destination page are updated (144). Finally, the V bit of the page table entry 40 corresponding to the transfer destination page is turned off to invalidate the page (145). Note that (141) to (145) constitute a page transfer means.

On the other hand, if there is no free page in LMS and there is one in GMS, transfer one page for LMS to GMS (147-15
2) After creating a free page, transfer the transfer page to the own LMS in the same manner as above. Here, when there is no free page in the GMS, in order to avoid frequent occurrence of pseudo page faults in subsequent accesses, the ebit of the page table entry is turned on to suppress the occurrence of faults.

The above is the memory management method for a multiprocessor system with distributed main memory.

Next, a method for allocating a process to an optimal CPU will be explained.

In a multiprocessor, deciding which processor to allocate to a process is an important process management task for the operating system. Normally, an operating system manages various types of data for each process, which serve as criteria for process selection, in the form of a process management table. Note that the term "process" here refers to the smallest unit to which processors are allocated.
Task is a synonym. Furthermore, in the sense of a unit of scheduling, threads in an operating system called MACH developed at Carnegie Mellon University in the United States can be considered equivalent. In this case,
The process management table can be read as a task management table and a thread management table, respectively.

FIG. 7 shows the contents of the process management table 50. The process management table includes various data such as priority in addition to the process status 51, but in this embodiment, not all of this is stored. 52 to 56 constitute process allocation information storage means, and 52 holds the number of pages allocated to the LMS of the CPU in the memory being used by this process. Here, a page is a physical memory divided into 4 KB units, and is the minimum unit of memory management. 52 to 55 are CPU2, respectively.
(7) in oB to 20D relates to LMS, and 56 holds equivalent information regarding GMS.

The determining means 57 is a field for specifying the type of scheduling, and the details will be explained in FIG. 8. 58 is a field that holds the number of times processor allocation was postponed due to the specification of the scheduling controller 57 even though it had the right to be executed next in terms of priority, and is reset to 0 every time a processor is allocated. do.

59 is a field indicating the upper limit value of the send-off counter. 60 is a field for specifying a processor to be assigned to this processor, and whether or not this field is used is determined by the scheduling controller 57.

Figure 9 shows the system call flow for setting arbitrary values to each of these feel routes from a program.
~72 requests the value of the argument respectively Processor number 60,
The scheduling controller 57 and send-off counter threshold value 59 are set. Note that when no system call is issued, the values of the scheduling controller 57 and the like are inherited by the child process.

FIG. 8 shows details of the scheduling controller (determining means). Control code O requests conventional scheduling. In other words, the process with the highest priority at the moment is given to the processor as the next process to execute. The meanings of control codes 1 to 7 are as shown in FIG. 8, respectively. Here, a candidate process is a process selected from the list of waiting processes to be executed next, and if it matches the conditions of the scheduling controller, it will be officially selected as the process to be executed next. given a processor.

FIG. 10 shows a processing flow when scheduling processes using the process management table shown in FIG. 7. First, it is checked whether the list of executable processes is empty (10). If it is empty, it naturally ends without doing anything and remains in an idle state (not shown) until an executable process is generated. When the list is not empty, the process with the highest priority is selected as a candidate process (11). Then, according to the scheduling controller, the candidate process is inspected (12) (described later), and if it meets the conditions, the processor executing this scheduling program is designated as the next process to be executed. . If the conditions are not met, the send-off counter is incremented and then the next candidate process is exited. FIGS. 11 to 14 show candidate processes.

The detailed flow of the inspection is shown. When the control code is 0, the dispatch request flag (ie, processor allocation request flag) is immediately turned on. If this flag is turned on, it is determined that the candidate process meets the conditions (90). When the control code is other than O, the respective determination processing is performed (82,
83, 84° 86. 87, 88). FIG. 12 shows a case where the scheduling control code is 1 or 5. In this case, all the memory nodes allocated to the candidate process exist in this LMS or GMS (9o), or because these conditions are not met, the number of times the candidate process is turned off is reached the threshold. When the value is exceeded (92), the dispatch request flag is turned on (91), and at other times, dispatch is seen (93). 2 control coats
Alternatively, in the case of 6.3 or 7, as shown in FIG. 13.14, almost the same processing as in FIG. 12 is performed.

By performing such scheduling, it is possible to allocate the CPU with the most data to the process, thereby shortening memory access time and reducing bus load.

〔Effect of the invention〕

According to the multiprocessor scheduling method of the present invention, the CPU that has the most programs or data related to the process can be assigned to the process, which makes it possible to shorten the average memory access time and increase the actual access speed of the processor. improves. Additionally, since the bus load can be reduced, bottlenecks in the entire system can be eliminated and performance can be improved.

Further, according to the present invention, as the program is executed, data in other CPUs can be transferred to the own CPU, which has the effect of gradually improving performance.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing a physical space memory, FIG. 3 is a diagram showing one entry of an address translation table, and FIG. 4 is a bus error detection circuit. Configuration diagram, Figure 5 shows the flow of Figure 4, Figure 6 shows the flow of pseudo page fault processing, Figure 7 shows the contents of the process management table, and Figure 8 shows the scheduling controller. FIG. 9 is a diagram showing the flow of system calls, FIG. 10 is a diagram showing the processing flow of FIG. 7, and FIGS. 11 to 14 are diagrams showing the inspection flow of candidate processes. . 20A, 20B-=CPU (central processing unit) 21...
Processor, 22...MMU (memory management unit), 23...LM
S27...Communication path, 29...GMS (main memory)
.

Claims (1)

[Claims] 1. A plurality of CPUs consisting of a plurality of processors and a main memory shared by each processor, each processor having a connection between its internal processor and other processors. In a multiprocessor process scheduling method in which mutual memory is freely accessible via a communication path and the process scheduler allocates one of the processors to an executable process according to the process management table, the process management table A process allocation information storage means for storing a list of main memories having programs or data to be executed, and a determining means for calculating a candidate process to be executed next using the process allocation information, and an output of the determining means. A multiprocessor process scheduling method, wherein the process scheduler allocates processors to processes according to the following. 2. The process allocation information storage means stores each CP
2. The multiprocessor process scheduling system according to claim 1, wherein the number of pages mapped to the main memory in the U and used for each process is stored for each CPU. 3. The determining means is the CP on which the process scheduler is operating.
2. The multiprocessor process scheduling method according to claim 1, wherein executable processes whose programs or data are all held in the main memory of U are calculated as candidates. 4. The determining means is the CP on which the process scheduler is operating.
2. The multiprocessor process scheduling method according to claim 1, wherein an executable process whose main memory in U has the largest number of programs or data is calculated as a candidate. 5. Equipped with a plurality of CPUs consisting of a plurality of processors and a main memory shared by each processor, each processor has a communication path that connects the internal processor and other processors In a multiprocessor process scheduling method in which mutual memory is freely accessible and a process scheduler assigns any processor to a process in an executable state according to a process management table, the process management table specifies in advance the processor to be assigned to each process. The process scheduler has a process allocation information storage means and a determining means for calculating a candidate process to be executed next using the process allocation information, and the process scheduler allocates a processor to a process according to the output of the determining means. A multiprocessor process scheduling method. 6. The multiprocessor scheduling method according to claim 5, wherein the process allocation information storage means holds an identifier of a processor to be allocated to each process. 7. The determining means calculates as candidates an executable process for which the process scheduler specifies an operating processor.The determining means calculates as a candidate an executable process for which the process scheduler specifies an operating processor. 6. The multiprocessor process scheduling method according to claim 5, wherein the multiprocessor process scheduling method is calculated. 8.Equipped with a plurality of CPUs consisting of a plurality of processors and a main memory shared by each processor, each CPU has a communication path that connects the internal processor and other processors In a memory management method for a multiprocessor that allows mutual memory to be freely accessed, external access detection means detects access to the main memory of another CPU and notifies the processor of the CPU that has generated the access; a communication means for communicating the output of the detection means to the operating system;
1. A multiprocessor memory management system, comprising page transfer means for transferring pages of an access target area to a main memory within its own CPU in accordance with an output of said transfer means. 9. The multiprocessor memory management system according to claim 8, wherein the external access detection means does not detect external access while the page transfer means is operating. 10. The page transfer means issues a request to the CPU having the page of the access target area to invalidate the access target area, and the CPU drops the valid flag of the access target area in accordance with the request. The multiprocessor memory management method according to item 8. 11. The multiprocessor memory management system according to claim 8, wherein the transmission means operates only when the transmission permission flag of the page management table of the access target area is valid.