JPS57120284A - High-speed buffer memory control system - Google Patents

High-speed buffer memory control system

Info

Publication number
JPS57120284A
JPS57120284A JP56006861A JP686181A JPS57120284A JP S57120284 A JPS57120284 A JP S57120284A JP 56006861 A JP56006861 A JP 56006861A JP 686181 A JP686181 A JP 686181A JP S57120284 A JPS57120284 A JP S57120284A
Authority
JP
Japan
Prior art keywords
speed buffer
buffer memory
control
program
information processor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56006861A
Other languages
Japanese (ja)
Other versions
JPS6046450B2 (en
Inventor
Hideo Hayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP56006861A priority Critical patent/JPS6046450B2/en
Publication of JPS57120284A publication Critical patent/JPS57120284A/en
Publication of JPS6046450B2 publication Critical patent/JPS6046450B2/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0846—Cache with multiple tag or data arrays being simultaneously accessible
    • G06F12/0848—Partitioned cache, e.g. separate instruction and operand caches

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE:To prevent a decrease in HIT rate even during program switching by providing two high-speed buffer memories and by loading the contents of a program to be executed next to one memory which is not in use at present. CONSTITUTION:An information processor which transfers the contents of a main storage device to a high-speed buffer memory temporarily and utilizes them is provided with two buffer memories. Under the control of control flags which show the operation states of the high-speed buffer memories, information on a program to be executed next by the information processor is transferred from the main storage device to one high-speed buffer memory which is not used by the information processor at present and when the control is passed to the program, the high-speed buffer memory is utilized. For example, two buffer memory control parts A and B constituted as shown by the figure, a control register 1, etc., are provided to perform said control.
JP56006861A 1981-01-19 1981-01-19 High-speed buffer memory control method Expired JPS6046450B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56006861A JPS6046450B2 (en) 1981-01-19 1981-01-19 High-speed buffer memory control method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56006861A JPS6046450B2 (en) 1981-01-19 1981-01-19 High-speed buffer memory control method

Publications (2)

Publication Number Publication Date
JPS57120284A true JPS57120284A (en) 1982-07-27
JPS6046450B2 JPS6046450B2 (en) 1985-10-16

Family

ID=11650016

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56006861A Expired JPS6046450B2 (en) 1981-01-19 1981-01-19 High-speed buffer memory control method

Country Status (1)

Country Link
JP (1) JPS6046450B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7644234B2 (en) 2004-05-31 2010-01-05 Sony Computer Entertainment Inc. Information processing apparatus with a cache memory and information processing method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7644234B2 (en) 2004-05-31 2010-01-05 Sony Computer Entertainment Inc. Information processing apparatus with a cache memory and information processing method

Also Published As

Publication number Publication date
JPS6046450B2 (en) 1985-10-16

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