JPS5730179A - Buffer memory control system - Google Patents

Buffer memory control system

Info

Publication number
JPS5730179A
JPS5730179A JP10469780A JP10469780A JPS5730179A JP S5730179 A JPS5730179 A JP S5730179A JP 10469780 A JP10469780 A JP 10469780A JP 10469780 A JP10469780 A JP 10469780A JP S5730179 A JPS5730179 A JP S5730179A
Authority
JP
Japan
Prior art keywords
address
fetch
data
buffer memory
store
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10469780A
Other languages
Japanese (ja)
Inventor
Matao Ito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP10469780A priority Critical patent/JPS5730179A/en
Publication of JPS5730179A publication Critical patent/JPS5730179A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE:To speed the handling of a MOVE instruction meeting specific requirements, by substituing the address part of a tag entry, which corresponds to data in a fetch-destination, by a store address. CONSTITUTION:When a MOVe instruction for transferring data in some area to another area is executed, a fetch-destination address 3 and a store-destination address 4 are compared 13 mutually and when byte address parts and line addresses of the both are equal and the remaining volume 11 of transferred data exceeds one line, the address part of a tag entry corresponding to the data of the fetch-destination address 3 fetched in a buffer memory 10 is substituted by the store address 4.
JP10469780A 1980-07-29 1980-07-29 Buffer memory control system Pending JPS5730179A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10469780A JPS5730179A (en) 1980-07-29 1980-07-29 Buffer memory control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10469780A JPS5730179A (en) 1980-07-29 1980-07-29 Buffer memory control system

Publications (1)

Publication Number Publication Date
JPS5730179A true JPS5730179A (en) 1982-02-18

Family

ID=14387660

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10469780A Pending JPS5730179A (en) 1980-07-29 1980-07-29 Buffer memory control system

Country Status (1)

Country Link
JP (1) JPS5730179A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0383097A2 (en) * 1989-02-14 1990-08-22 Hitachi, Ltd. Cache memory
EP0589661A1 (en) * 1992-09-24 1994-03-30 International Business Machines Corporation Memory access

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0383097A2 (en) * 1989-02-14 1990-08-22 Hitachi, Ltd. Cache memory
EP0589661A1 (en) * 1992-09-24 1994-03-30 International Business Machines Corporation Memory access

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