JPS56135260A - Inter-processor information transfer system - Google Patents

Inter-processor information transfer system

Info

Publication number
JPS56135260A
JPS56135260A JP3707380A JP3707380A JPS56135260A JP S56135260 A JPS56135260 A JP S56135260A JP 3707380 A JP3707380 A JP 3707380A JP 3707380 A JP3707380 A JP 3707380A JP S56135260 A JPS56135260 A JP S56135260A
Authority
JP
Japan
Prior art keywords
information
memory
address
processor
sends
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3707380A
Other languages
Japanese (ja)
Other versions
JPS6053901B2 (en
Inventor
Kazunori Fujita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP55037073A priority Critical patent/JPS6053901B2/en
Publication of JPS56135260A publication Critical patent/JPS56135260A/en
Publication of JPS6053901B2 publication Critical patent/JPS6053901B2/en
Expired legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/16Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163Interprocessor communication
    • G06F15/167Interprocessor communication using a common memory, e.g. mailbox

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Information Transfer Systems (AREA)
  • Exchange Systems With Centralized Control (AREA)

Abstract

PURPOSE:To perform information transfer between processors rapidly by transferring information via a temporary memory the processors can control direct. CONSTITUTION:Processor 11 discriminates data stored in program memory 14 to send address information on temporary memory 32 onto address bus 13, and then sends information to be transferred onto data bus 12. The address information is sent to memory 32 via address discriminating circuit 17. The transfer information sent via bus 12 is also sent to memory 32. Next, processor 21 sends the address information on memory 32 onto address bus 23 and opens gate circuit 25 to sends the address information to memory 32. On the other hand, memory 32 sends information stored in the assigned address to processor 21. Thus, the inter-processor information transfer is carried out easily and rapidly.
JP55037073A 1980-03-24 1980-03-24 Inter-processor information transfer method Expired JPS6053901B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55037073A JPS6053901B2 (en) 1980-03-24 1980-03-24 Inter-processor information transfer method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55037073A JPS6053901B2 (en) 1980-03-24 1980-03-24 Inter-processor information transfer method

Publications (2)

Publication Number Publication Date
JPS56135260A true JPS56135260A (en) 1981-10-22
JPS6053901B2 JPS6053901B2 (en) 1985-11-27

Family

ID=12487368

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55037073A Expired JPS6053901B2 (en) 1980-03-24 1980-03-24 Inter-processor information transfer method

Country Status (1)

Country Link
JP (1) JPS6053901B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0411083Y2 (en) * 1987-08-06 1992-03-18

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5436138A (en) * 1977-08-26 1979-03-16 Nec Corp Direct memory access system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5436138A (en) * 1977-08-26 1979-03-16 Nec Corp Direct memory access system

Also Published As

Publication number Publication date
JPS6053901B2 (en) 1985-11-27

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