JPS5746374A - Address conversion pair control system - Google Patents

Address conversion pair control system

Info

Publication number
JPS5746374A
JPS5746374A JP55122726A JP12272680A JPS5746374A JP S5746374 A JPS5746374 A JP S5746374A JP 55122726 A JP55122726 A JP 55122726A JP 12272680 A JP12272680 A JP 12272680A JP S5746374 A JPS5746374 A JP S5746374A
Authority
JP
Japan
Prior art keywords
information
address conversion
cash
conversion pair
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP55122726A
Other languages
Japanese (ja)
Other versions
JPS6049349B2 (en
Inventor
Kiyoshi Morishima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP55122726A priority Critical patent/JPS6049349B2/en
Publication of JPS5746374A publication Critical patent/JPS5746374A/en
Publication of JPS6049349B2 publication Critical patent/JPS6049349B2/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE:To realize both the cash coincidence process and the invalidation of address conversion pair without increasing the hard quantity, by performing the invalidation of address conversion pair making use of the cash coincidence processing interface line. CONSTITUTION:The system consists of information processors 1-3, a main storage 5, cash coincidence processing interface lines CIL6-CIL11, registers 13 and 15 that hold the cash coincidence processing information or the address conversion pair control information and send it to the lines CIL6-CIL11, registers 16, 6 and 11 that hold the output of an information selecting circuit 19 on the CIL8 and CIL10, a register 17 that holds the output of an information selecting circuit 20, and a register 18 that holds the output of a selecting circuit 21 for the information of CIL9 and CIL7 respectively.
JP55122726A 1980-09-04 1980-09-04 Address translation versus control method Expired JPS6049349B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55122726A JPS6049349B2 (en) 1980-09-04 1980-09-04 Address translation versus control method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55122726A JPS6049349B2 (en) 1980-09-04 1980-09-04 Address translation versus control method

Publications (2)

Publication Number Publication Date
JPS5746374A true JPS5746374A (en) 1982-03-16
JPS6049349B2 JPS6049349B2 (en) 1985-11-01

Family

ID=14843061

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55122726A Expired JPS6049349B2 (en) 1980-09-04 1980-09-04 Address translation versus control method

Country Status (1)

Country Link
JP (1) JPS6049349B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59112356A (en) * 1982-12-20 1984-06-28 Yamatake Honeywell Co Ltd Controlling system of multiprocessor system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59112356A (en) * 1982-12-20 1984-06-28 Yamatake Honeywell Co Ltd Controlling system of multiprocessor system

Also Published As

Publication number Publication date
JPS6049349B2 (en) 1985-11-01

Similar Documents

Publication Publication Date Title
DE3485527D1 (en) DATA PROCESSING SYSTEM BUS WITH ERROR CYCLE OPERATION.
ES458222A1 (en) Common polling logic for input/output interrupt or cycle steal data transfer requests
JPS52119832A (en) Electroinc calculator of microprogram control system
JPS5319728A (en) Data treansfer processing system
JPS5318931A (en) Information processor
JPS5746374A (en) Address conversion pair control system
JPS52139333A (en) Data input system for cash register
JPS56135261A (en) Interprocessor information transfer system
JPS5746373A (en) Address conversion pair control system
JPS51144137A (en) Input/output data control unit
JPS5216942A (en) Information management method for electronic cash register
JPS5339022A (en) Information process unit
JPS52130256A (en) Information processing unit
JPS5337341A (en) Information processor
JPS526031A (en) Information processing unit
JPS5746372A (en) Address conversion pair control system
JPS5324744A (en) Information transfer system
JPS53103332A (en) Input/output control system for information processor
JPS55157027A (en) Input and output transfer control unit
JPS5339032A (en) Branch control system
JPS56135260A (en) Inter-processor information transfer system
JPS55108068A (en) Memory control system
JPS51127644A (en) Bill processing system
JPS5419615A (en) Control system for input and output unit
JPS51128590A (en) Data processing system for analizer