JPS5746374A - Address conversion pair control system - Google Patents
Address conversion pair control systemInfo
- Publication number
- JPS5746374A JPS5746374A JP55122726A JP12272680A JPS5746374A JP S5746374 A JPS5746374 A JP S5746374A JP 55122726 A JP55122726 A JP 55122726A JP 12272680 A JP12272680 A JP 12272680A JP S5746374 A JPS5746374 A JP S5746374A
- Authority
- JP
- Japan
- Prior art keywords
- information
- address conversion
- cash
- conversion pair
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Multi Processors (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Abstract
PURPOSE:To realize both the cash coincidence process and the invalidation of address conversion pair without increasing the hard quantity, by performing the invalidation of address conversion pair making use of the cash coincidence processing interface line. CONSTITUTION:The system consists of information processors 1-3, a main storage 5, cash coincidence processing interface lines CIL6-CIL11, registers 13 and 15 that hold the cash coincidence processing information or the address conversion pair control information and send it to the lines CIL6-CIL11, registers 16, 6 and 11 that hold the output of an information selecting circuit 19 on the CIL8 and CIL10, a register 17 that holds the output of an information selecting circuit 20, and a register 18 that holds the output of a selecting circuit 21 for the information of CIL9 and CIL7 respectively.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55122726A JPS6049349B2 (en) | 1980-09-04 | 1980-09-04 | Address translation versus control method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55122726A JPS6049349B2 (en) | 1980-09-04 | 1980-09-04 | Address translation versus control method |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5746374A true JPS5746374A (en) | 1982-03-16 |
JPS6049349B2 JPS6049349B2 (en) | 1985-11-01 |
Family
ID=14843061
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP55122726A Expired JPS6049349B2 (en) | 1980-09-04 | 1980-09-04 | Address translation versus control method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6049349B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59112356A (en) * | 1982-12-20 | 1984-06-28 | Yamatake Honeywell Co Ltd | Controlling system of multiprocessor system |
-
1980
- 1980-09-04 JP JP55122726A patent/JPS6049349B2/en not_active Expired
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59112356A (en) * | 1982-12-20 | 1984-06-28 | Yamatake Honeywell Co Ltd | Controlling system of multiprocessor system |
Also Published As
Publication number | Publication date |
---|---|
JPS6049349B2 (en) | 1985-11-01 |
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