JPS6049349B2 - Address translation versus control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an address translation pair control method for a multiprocessor system that shares a plurality of information processing devices that employ a virtual memory method.

Generally, in an information processing device that uses a virtual memory method,
The correspondence between the virtual address pointing to the virtual memory space and the real address in the real memory space is registered in the address translation pair buffer in the processing unit, so that the address translation table in the main memory is not referenced every time the main memory is referenced. The address translation pair buffer is utilized to perform translation from a virtual address to a real address in a short time. Further, if data has not yet been transferred from the external storage device to the area on the main memory that the processing device attempts to refer to, the data is transferred from the external storage device to the main storage device. At this time, if there are no empty pages in the main memory to newly import data from the external storage device, pages that are no longer used or are used infrequently are swapped out to the external storage device,
An empty area is secured on the main memory, and new data is swapped in from the external storage device into that area. When multiple information processing devices that use virtual memory share the same main memory, the page-corresponding address that one information processing device attempts to swap out is registered in the address translation buffer in the other information processing device. There are some things that have been done. As described above, when referring to the main memory, the information processing device checks whether the target address translation pair is registered in the address translation pair buffer, and if so, uses its real address. Therefore, if one information processing device swaps out a page with an address registered in the address translation buffer of the other information processing device, the other information processing device will no longer be able to use the correct information. . Therefore, in conventional information processing apparatuses, this problem is dealt with as follows. (1)
Before swapping out an area on main memory, one information processing device issues an external interrupt to the other information processing device via a dedicated control line, and the other information processing device converts the address using an external interrupt program. After invalidating the pair, one information processing device is notified of the termination of the external interrupt program processing via a dedicated control line.

One of the information processing devices executes swap-out only after receiving this notification. (2) When one information processing device swaps out an area on the main memory, address information indicating the area is stored at a specific address on the main memory, and the other processing device refers to the specific address on the main memory. Among the registered address translation pairs in the processing device, only the corresponding translation pair is made valid.

However, method (1) requires an external interrupt to be applied to all connected information processing devices each time a swap-out is performed, and the number of dedicated control lines increases with the number of connected information processing devices. However, the disadvantage is that the amount of hardware increases. Furthermore, method (2) has the disadvantage that every time a certain information processing device performs five swap-outs, other information processing devices must access the main memory, so that the processing time is long. Furthermore, in a multiprocessor system consisting of a plurality of information processing devices each having a buffer storage device (cache), when one information processing device rewrites an area in the main memory, the area is written to the cache of another information processing device. is registered, the corresponding part of the cache must be cleared.

If it is not erased, data different from data 3 in the main memory will be registered on the cache, and correct processing will no longer be possible. For this reason, conventionally, a special interface line called an interface line for cache match processing is provided between information processing devices for the above-mentioned erasure, and this interface line is separate from normal data transfer. has been
The disadvantage is that the amount of hardware is large considering the frequency of use.
SUMMARY OF THE INVENTION It is an object of the present invention to provide an address translation control system that eliminates the above-mentioned drawbacks.

The system of the present invention includes a main storage device, an address translation pair buffer that shares the main storage device and stores a plurality of address translation pairs consisting of circular address information and physical address information of the main storage device, and instructions for specific instructions. The address of the main storage device is connected to an interface line for instructing to erase the storage contents of the cache memory of another information processing device when one information processing device rewrites the storage contents of the main storage device. a first information processing device having means for transmitting information; and an address translation pair buffer that shares the main storage device and stores a plurality of address translation pairs each consisting of logical address information and physical address information of the main storage device. and only the specified address translation/translation pair out of the plurality of address translation pairs stored in the address translation buffer is determined by the address information sent from the first information processing device via the interface line. and a second information processing device having invalidation means.

Next, the present invention will be explained in detail with reference to the drawings.

An embodiment of the present invention shown in FIG.
and 3, main memory 5, cache match processing interface lines 6, 7, 8, 9, 10 and 11, cache match processing interface that holds either cache match processing information or address translation pair control information. registers 13, 14 and 15 for sending to lines 6 to 11; a selection circuit 19 for selecting one of the information on interface lines 8 and 10 for cache match processing;
A register 16 that holds the output of the selection circuit 19, a selection circuit 20 that selects one of the information on interface lines 6 and 11 for cache match processing, a register 17 that holds the output of the selection circuit 20, and an interface for cache match processing. A selection circuit 21 that selects one of the information on lines 9 and 7, a register 18 that holds the output of the selection circuit 21, information processing devices 1, 2, and 3, and a main memory 5
It consists of interface lines 52, 53, and 54 between.

The information processing apparatuses 1, 2, and 3i shown in FIG. 2 each have a register 22 that holds a part of the address translation control address information received by the register 16, 17, or 18 of FIG. According to the contents of register 23, address translation pair buffer 24, which has n virtual addresses, n real addresses corresponding thereto, and a bit (V bit) indicating the validity of the translation pairs, for the number n of translation pairs. A comparison circuit 25 that compares the virtual address of the pointed address translation pair with the contents of the register 22, and a register 26 that sets the bit to ゜゜1゛/゜“0゛” in order to enable/enable the address translation pair. and an AND circuit 27 which performs a logical product of the output of the comparison circuit 25 and the ■ bit.

Next, the operation of swapping out pages on the information processing device 1 and the main memory 5 to the external storage device will be explained in detail.

The information processing device 1 holds in the register 13 a virtual address indicating the area of the virtual space to be swapped out.

This virtual address is transferred to the information processing devices 2 and 3 via the cache match processing interface lines 6 and 9. The information processing devices 2 and 3 select the transferred virtual addresses using selection circuits 20 and 21 and hold them in registers 17 and 18. Furthermore, it is checked whether this virtual address is registered in its own address translation pair buffer 24. That is, part of the virtual address stored in register 17 or 18 is stored in register 22, and the rest is stored in register 23. The contents of the register 23 are given as an address to the address translation pair buffer 24, and the corresponding virtual address is read out. This read virtual address and the contents of the register 22 are compared to the comparison circuit 25.
compared by. At the same time, the V bit is also read out, and the AND circuit 27 performs a logical product between the output of the comparator circuit 25 and the ■ bit. The output of the AND circuit 27 is “゜1
゛ indicates that the corresponding address translation pair is registered. If the output of the AND circuit 27 is "1", the register 2
6 is taken in as ``0'', and the contents of the register 26 are written to the corresponding V bits, invalidating the address translation pair.If the output of the AND circuit 27 is ゜゜0゛, If there is, the corresponding virtual address is not registered, so nothing is done.In this way, when the invalidation of the corresponding address translation pair is completed in the information processing devices 2 and 3, the information processing devices 2 and 3 complete the invalidation of the corresponding address translation pair. 3 writes end information in a specific area of the main memory 5. After transferring the address information, the information processing device 1 frequently reads the contents of the specific area of the main memory 5 to check whether end information has been written. The information processing device 1 performs swap-out only after confirming that the end information has been written.The present invention includes the use of an interface line for cache matching processing to perform address translation and invalidation. Since no unique interface line is provided for address translation vs. invalidation, the amount of hardware does not increase, and the cache match processing interface can be used for two purposes: cache matching processing and address translation vs. invalidation. This method has the advantage that it can be processed in a shorter time than the method of writing the corresponding address in the main memory.

q Brief Description of the Drawings FIG. 1 is a diagram showing one embodiment of the present invention, and FIG. 2 is a diagram showing an address translation pair buffer.

In Figures 1 and 2, 1, 2, 3...
Information processing device, 5... Main memory, 76, 7, 8.
...Data transfer line, 9, 10, 11...
・Interface line for cache matching processing, 13
, 14, 15, 16, 17, 18, 22, 23...
・Lujistar, 19, 20, 21...Switching circuit, 2
4...Address conversion vs. buffer, 255...
・Comparison circuit, 26...Flip-flop, 52,5
3, 54...Interface line between information processing device and main memory.

Claims (1)

[Scope of Claims] 1. In an address conversion pair control method for a multiprocessor system without a system control device, a main storage device, and logical address information and physical address information of the main storage device that share this main storage device. an address translation pair buffer that stores a plurality of address translation pairs consisting of; and an address translation pair buffer that stores a plurality of address translation pairs consisting of; a first information processing device having means for sending address information of the main storage device to an interface line for instructing erasure; and a first information processing device that shares the main storage device and transmits logical address information and physical address information of the main storage device. an address translation pair buffer that stores a plurality of address translation pairs consisting of information; and a plurality of addresses stored in the address translation buffer based on address information sent from the first information processing device via the interface line. and a second information processing device having means for invalidating only the specified address translation pair among the translation pairs.