JPS6049348B2 - Address translation versus control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an address translation pair control method for a multiprocessor system in which a main memory is shared by a plurality of information processing devices that employ a virtual storage method.

Generally, in an information processing device that uses a virtual memory method,
The correspondence between the virtual address pointing to the virtual memory space and the real address in the real memory space is registered in the address translation pair buffer in the processing unit, so that the address translation table in the main memory is not referenced every time the main memory is referenced. The address translation pair buffer is utilized to perform translation from a virtual address to a real address in a short time.

Furthermore, if data from the external storage device has not yet been transferred to the area on the main memory that the processing device attempts to refer to, the data is transferred from the external storage device to the main storage device.
At this time, if there is no empty page in the main memory to newly import data from the external storage device, pages that are no longer used or are used infrequently are slipped out to the external storage device and are stored in the main memory. An empty area is secured and new data is swapped in from the external storage device into that area. When multiple information processing devices using the virtual memory method share the same main memory, a page-compatible address that one information processing device attempts to swap out may be sent to the address translation buffer in another information processing device. It may be registered. As described above, when referring to the main memory, the information processing device checks whether the target address translation pair is registered in the address translation pair buffer, and if so, uses its real address. Therefore, if one information processing device swaps out a page with an address registered in the address translation buffer of the other information processing device, the other information processing device will no longer be able to use the correct information. . Therefore, in conventional information processing apparatuses, this problem is dealt with as follows. (1) Before swapping out an area on main memory, one information processing device sends a message to another information processing device.
An external interrupt is applied via a dedicated control line, and the other information processing device disables the address translation pair using an external interrupt program, and then an external interrupt program is sent to one information processing device via a dedicated control line to terminate processing of the external interrupt program. to contact you.

One of the information processing devices executes swap-out only after receiving this notification. (2) When one information processing device swaps out an area on the main memory, it stores address information indicating the area at a specific address on the main memory,
Other processing devices refer to the specific address in the main memory and invalidate only the corresponding translation pair among the address translation pairs registered in the processing device.

However, method (1) requires an external interrupt to be applied to all connected information processing devices each time a swap-out is performed, and the number of dedicated control lines increases with the number of connected information processing devices. However, the disadvantage is that the amount of hardware increases. The method (2) also applies to certain information processing devices. Each time a device performs a swap-out, other information processing devices must access the main memory, which has the disadvantage of a long processing time. In addition, a multiprocessor system consisting of a plurality of processing units having a buffer storage device (cache). In the system, when an information processing device rewrites an area on the main memory, if the area is registered in the cache of another information processing device, the corresponding portion of the cache must be erased. If it is not erased, data different from the data in the main memory will be registered on the cache, and correct processing will no longer be possible. For this purpose, a special interface line called an interface line for cache match processing has conventionally been provided between information processing apparatuses for the above-mentioned erasure. This interface line is provided separately from normal data transfer, and has the disadvantage that the amount of hardware is large considering its frequency of use. An object of the present invention is to provide an address translation control method that eliminates the above-mentioned drawbacks. The control method of the present invention includes a first information processing device, a second information processing device having a cache memory, a main storage device shared by these devices, and the main storage device and the second information processing device. and an interface line for instructing to erase the storage contents of the cache memory of the second information processing device when the first information processing device rewrites the storage contents of the main storage device. In the address translation pair control method for a system comprising: It has means for sending address information of a main storage device, and the main storage device transfers the address information sent from the first information processing device to the second information processing device via the interface line. the second information processing device includes an address translation pair buffer that stores a plurality of address translation pairs each consisting of logical address information and physical address information of the main storage device; and an address supplied via the interface line. The present invention is characterized by comprising means for invalidating only the designated address translation pair among the plurality of address translation pairs stored in the address translation buffer based on information.

Next, the present invention will be explained in detail with reference to the drawings.

An embodiment of the present invention shown in FIG. 1 includes information processing devices 1, 2, and 3 having address translation pairs, a main memory 5, data transfer lines 6, 7, and 8, a cache match processing interface line, 9, 10 and 11, registers 13, 14 and 15 for holding either cache match processing information or address translation pair control address information and transmitting it to data transfer lines 6, 7 and 8, for cache match processing; Registers 16, 17 and 18 that receive either information or the difference between address translation and control address information from cache match processing interfaces 9, 10 and 11, and information on data transfer lines 7 and 8, are selected and cached. Selection circuit 19 and data transfer lines 6 and 8 that send data to the interface line 9 for shoe matching processing
The selection circuit 20 selects any of the above information and sends it to the cache match processing interface line 10, and selects any of the information on the data transfer lines 6 and 7 and sends it to the cache match processing interface line 11. It is comprised of a selection circuit 21 that sends out signals to

The information processing devices 1, 2 and 3 shown in FIG.
A register 22 holds part of the address translation control address information received in registers 16, 17, or 18 in the figure, a register 23 holds the remainder, n virtual addresses and n corresponding addresses. The number n of exchange pairs of the bit (V bit) indicating the validity of the real address and its translation pair
Address translation pair buffer 24, register 23 having only
The comparison circuit 25 compares the virtual address of the address translation pair pointed to by the contents of the register 22 with the contents of the register 22, and sets the ■ bit to “1”/in order to enable/disable the address translation pair.
Register 26 and comparator circuit 25 for setting “゜0゛”
It is composed of an AND circuit 27 that performs a logical product of the output of and the ■ bit.

Next, the operation of the information processing device 1 to swap out pages on the main memory 5 to the external storage device will be explained in detail.

The information processing device holds in the register 13 a virtual address indicating the area of the virtual space to be swapped out.

This virtual address is transferred to main memory 5 via data transfer line 6. The main memory 5 selects the transferred virtual address using the selection circuits 20 and 21 and transfers it to the information processing devices 2 and 3 on the cache match processing interface lines 10 and 11. Information processing devices 2 and 3 receive the virtual address in registers 17 and 18, respectively, and check whether it is registered in their address exchange pair buffer 24. That is, part of the virtual address stored in register 17 or 18 is stored in register 22, and the rest is stored in register 23. The contents of the register 23 are given as an address to the address translation pair buffer 24, and the corresponding virtual address is read out. The read virtual address and the contents of the register 22 are compared by a comparison circuit 25. At the same time, the ■ bit is also read out, and the address circuit 27 performs an AND operation between the output of the comparator circuit 25 and the V bit. If the output of the AND circuit 27 is “゜1”, it indicates that the corresponding address conversion pair is registered. If the output of the AND circuit 27 is “゜1”, the "0" is taken into the register 26, and the contents of the register 26 are written to the corresponding bit, invalidating the address translation pair.If the output of the AND circuit 27 is ゜゜0゛If so, the corresponding virtual address is not registered, so nothing is done.In this way, when the invalidation of the corresponding address translation pair is completed in the information processing devices 2 and 3, the information processing device 2 and 3 writes termination information to a specific area of the main storage device 5. After the address information is transferred, the information processing device frequently reads the contents of the specific area of the main storage device 5 to check whether termination information has been written. Check. Information processing device 1
performs swapout only after confirming that termination information has been written. In the present invention, by performing address translation pair invalidation using a cache match processing interface line, cache match processing and address translation pair invalidation can be performed instead of providing a unique interface line for address translation pair invalidation. The cache match processing interface is used for two purposes:
This method has the advantage that processing can be accomplished in a shorter time compared to a method configuration in which the corresponding address is written in the main memory.

[Brief explanation of the drawing]

7 FIG. 1 is a diagram showing one embodiment of the present invention, and FIG. 2 is a block diagram showing an address translation pair buffer. 1 and 2, 1, 2, 3...information processing device, 4...system control device, 5...O
Main memory, 6, 7, 8... Data transfer line, 9
, 10, 11... Interface line for cache match processing, 13, 14, 15, 16, 17, 18
, 22, 23...Register, 19, 20, 21
...Switching circuit, 24...Address conversion pair buffer, 25...Comparison circuit, 26...Flip-flop.

Claims (1)

[Claims] 1 A first information processing device that does not have a system control device, a second information processing device that has cache memory, a main storage device shared by these devices, and the main storage device and the second information processing device. an interface line for connecting with a processing device and instructing to erase the storage contents of the cache memory of the second information processing device when the first information processing device rewrites the storage contents of the main storage device; In an address translation versus control scheme for a system having
The first information processing device includes an address translation pair buffer that stores a plurality of address translation pairs consisting of logical address information and physical address information of the main storage device, and means for sending address information of the main storage device. , the main storage device has means for transferring address information sent from the first information processing device to the second information processing device via the interface line, the second information processing device an address translation buffer that stores a plurality of address translation pairs consisting of logical address information and physical address information of the main memory; and a plurality of address translation pairs stored in the address translation buffer based on address information supplied via the interface line. An address translation pair control method comprising means for invalidating only the specified address translation pair among the address translation pairs.