JPH0731310Y2 - Memory device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory device, and more particularly, to a memory device including a buffer memory device and an address translation device.

(Prior Art) A buffer memory device stores an address output by a CPU and data on a main storage device corresponding to the address,
It is provided in the memory device for the purpose of completing the memory access of the CPU at high speed.

FIG. 2 is a block diagram of an example of a conventional memory device having a buffer memory device and an address translation device.

In the figure, reference numeral 5 indicates an address line and reference numeral 6 indicates a data line.

The address output from the CPU 1 is output to the buffer memory device 2 and the address conversion device 3 via the address line 5, and if the data corresponding to the address is stored in the buffer memory device 2, the data is stored. Is read from the buffer memory device 2.

If not stored, the address is output to the main storage device 4 via the address conversion device 3, the data corresponding to the address is read from the main storage device 4, and the address and data are stored in the buffer memory device. It is stored in 2.

Usually, such a buffer memory device is called a cache memory, and hereinafter, the buffer memory device refers to a cache memory.

By the way, when the address translation table (not shown) in the address translation device 3 is switched, the data storage area in the main memory device 4 corresponding to the address output by the CPU 1 changes, so that the data is output from the CPU 1. The correspondence between the address stored in the buffer memory device 2 and the data stored in the buffer memory device 2 is lost, and the data stored in the buffer memory device 2 becomes meaningless.

Therefore, it is necessary to clear all the data in the buffer memory device 2 (hereinafter referred to as invalidating the data) so that the CPU 1 does not accidentally extract the data stored in the buffer memory device 2.

The buffer memory device is disclosed in, for example, Japanese Patent Laid-Open No. 55-44650, and the address translation device is described in, for example, Japanese Patent Laid-Open No. 59-14184.
It is described in Japanese Patent Publication No.

In addition to such a memory device, an address and a table identifier for identifying an address conversion table are stored in the buffer memory, and data corresponding to a plurality of address conversion tables are stored in the same block of the buffer memory. There is also proposed a memory device that stores data in a memory.

(Problems to be Solved by the Invention) The conventional techniques described above have the following problems.

(1) As described above, in the conventional memory device as shown in FIG. 2, it is necessary to invalidate the data in the buffer memory device when the address translation table in the address translator is switched. However, the invalidation of the data conflicts with the original purpose of the buffer memory device, and the use efficiency of the buffer memory device decreases.

That is, the buffer memory device accumulates the data in the main storage device read by the CPU, and when the corresponding data is stored in the buffer memory device,
However, if the data in the buffer memory device is invalidated, the accumulated data will be erased as described above, and even if the address translation table is used as it was, Even if it is switched to, the data must be newly stored in the buffer memory device. And until this accumulation is made, CP
The U memory access cannot be completed at high speed.

Further, when the CPU invalidates the above-mentioned data based on a predetermined program, the processing amount of the CUP increases, and the calculation speed for performing the originally required processing becomes slower. There is a risk.

(2) In a memory device in which addresses and table identifiers are stored in a buffer memory and data corresponding to a plurality of address conversion tables are stored in the same block in the buffer memory, for example, the same address conversion table is used. When the data in the main storage device is accessed over a wide range of storage space using, and only the data corresponding to the address conversion table is stored in the buffer memory device, the address conversion table is switched. Most of that data will have to be invalidated.

As a result, the use efficiency of the buffer memory device is reduced and the operation speed of the CPU is reduced, as in the case described above with respect to (1).

The present invention has been made to solve the above problems.

(Means and Actions for Solving Problems) A plurality of cache memory (buffer memory) blocks corresponding to a plurality of address conversion tables are provided, the address conversion tables are switched, and a cache memory (buffer memory) corresponding to the address conversion tables is provided. ) The point is that it is switched to the block.

This eliminates or reduces the need to invalidate the buffer memory block each time the address conversion table is switched, improving the efficiency of use of the buffer memory device and preventing the CPU processing speed from decreasing. The effect of being able to do so can be produced.

(Example) Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a schematic block diagram of an embodiment of the present invention. In FIG. 1, the same reference numerals as those in FIG. 2 represent the same or equivalent parts.

In FIG. 1, reference numeral 25 is an address line, and reference numeral 26
Indicates a data line.

The address translation device 3 uses the first address translation table 3
It is provided with N address conversion tables from -1 to the Nth address conversion table 3-N.

The buffer memory devices 15 have the same size (capacity) and the same number as the address conversion tables in the address conversion device 3, that is, N buffer memory blocks (first buffer memory blocks 15-1 to 15-1 to 15-2). An Nth buffer memory block 15-N) is provided. Each address line of each address conversion table is
One-to-one connection is made to the address lines of each address conversion table in the address conversion device 3. That is, the first buffer memory block 15-1 is added to the first address conversion table 3-1 and the second buffer memory block 15-2 is added.
Is connected to the second address conversion table 3-2, and the Nth buffer memory block 15-N is connected to the Nth address conversion table 3-N.

An address line 25 connecting each address conversion table and each buffer memory block is connected to the switching mechanism 12.

The switching mechanism 12 selects only one set of each buffer memory block and address conversion table by the control signal output from the CPU 11 via the switching register 14,
Connect to U11.

The first to Nth address conversion tables 3-1 to 3-1
-N is connected to the main storage device 4 via the main storage interface 13.

The main memory interface 13 selects any one of the address conversion tables 3-1 to 3-N according to a control signal output from the CPU 11 via the switching register 14, and selects the address line 25 as the main memory interface. Connect to the storage device 4.

The address line 25 of the CPU 11 is connected to the switching mechanism 12 and the data line 2
6 is the first to Nth buffer memory blocks 15-
1 to 15-N and the main memory 4, and the control signal line 27 is connected to the switching register 14.

The first to Nth buffer memory blocks 15
Since each of -1 to 15-N has the same size (capacity), it is possible to provide only one address comparison mechanism (tag unit) and share them.

In one embodiment of the present invention having the above configuration, first,
An address for reading data is output from the CPU 11 to the switching mechanism 12 via the address line 25, and a control signal designating an address conversion table and a buffer memory block to be selected is transmitted via the switching register 14 to the switching mechanism. 12 and the main memory interface 13.

Here, the first buffer memory block 15-1 and the first buffer memory block 15-1
It is assumed that the address conversion table 3-1 is selected.

By the output of the control signal, the switching mechanism 12 causes the CPU 11
Address line 25 of the first buffer memory block 15-
1 and the first address translation table 3-1 and
The addresses output from the CPU 11 are given to them.

Further, by the output of the control signal, the main memory interface 13 causes the first address conversion table 3-1 to
It is connected to the main storage device 4 via the main storage interface 13.

When the data corresponding to the address is stored (hit) in the first buffer memory block 15-1, the data stored in the buffer memory block 15-1 is read by the CPU 11. .

On the other hand, when the data corresponding to the address is not stored in the first buffer memory block 15-1 (missing), the first address conversion table 3-1 outputs the data from the CPU 11. Address is converted, the data stored in the main memory 4 is read by the converted address, and the data is stored in the first buffer memory block 15-1.

Unless the address conversion table 3-1 in the address conversion device 3 is switched, the data read from the main storage device 4 is stored in the first buffer memory block 15-1.

Here, a control signal for selecting a table (for example, a second address conversion table 3-2) different from the first address conversion table 3-1 is sent from the CPU 11 via the switching register 14 to the control signal. When output to the switching mechanism 12 and the main memory interface 13, not only the address conversion table but also the buffer memory block is divided into blocks corresponding to the second address conversion table 3A (that is, the second buffer memory block 15B). Because it will change
There is no risk that the data stored in the first buffer memory block 15-1 will be read out, and there is no need to invalidate the data in the first buffer memory block 15-1.

Therefore, even when the first buffer memory block 15-1 is selected again, the data accumulated in the past can be used as it is.

Of course, when the contents themselves of the address conversion table are rewritten, it can be dealt with by invalidating the entire contents of the corresponding buffer memory block.

In the above description, the buffer memory blocks 15-1 to 15-N have the same capacity, but the present invention is not limited to this, and the present invention is not limited thereto. It goes without saying that the capacity of each buffer memory block may be changed according to the field of use of the information processing apparatus to which is applied. In this case, the address comparison mechanism or the like may be provided for each buffer memory block.

Also, the buffer memory block is described as being provided in the same number as the number of the address conversion tables so as to correspond to each of the address conversion tables. However, the present invention is not particularly limited to this and two address conversion tables may be used. One buffer memory block may be provided for a plurality of address conversion tables, such as one buffer memory block for a table or one buffer memory block for three address conversion tables. Is natural.

(Effect of the Invention) As is apparent from the above description, according to the present invention, the buffer memory device is divided into a plurality of blocks, and when the address conversion table is switched, the blocks are also switched. The effect like is achieved.

(1) It is not necessary to invalidate the block of the buffer memory device every time the address conversion table is switched.

Therefore, the use efficiency of the buffer memory device does not decrease, and the calculation speed of the CPU does not decrease.

(2) In particular, in an information processing device in which a plurality of programs are executed in parallel (multitasking), the frequency of invalidation of the buffer memory device can be suppressed as much as possible even when the address conversion table is frequently switched. It becomes possible and a high hit rate can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention. FIG. 2 is a schematic block diagram of a memory device having a conventional buffer memory device. 3 ... Address translation device, 3-1 to 3-N ... First to Nth address translation table, 4 ... Main storage device, 11 ...
CPU, 12 ... Switching mechanism, 13 ... Main memory interface, 14 ... Switching register, 15 ... Buffer memory device,
15-1 to 15-N ... First to Nth buffer memory blocks, 25 ... Address line, 26 ... Data line, 27 ... Control signal line

Claims (3)

[Scope of utility model registration request] 1. An address translation device having a plurality of address translation tables for translating an address output from a main memory device and a CPU so as to correspond to an address in the main memory device, and an output from the CPU. A memory device having a cache memory device directly accessed by the address, wherein the cache memory device is composed of a plurality of cache memory blocks corresponding to the plurality of address conversion tables, according to a command from the CPU, A memory device comprising switching means for switching the address conversion table and switching to the cache memory block corresponding to the address conversion table. 2. The memory device according to claim 1, wherein the cache memory blocks have the same capacity. 3. A switching mechanism for switching an address line between a CPU and an address conversion table and a cache memory block corresponding to each other, and an address line between the address conversion table and the main memory device. 3. The memory device according to claim 1, wherein the memory device comprises a main memory interface for switching and a switching register for controlling the switching mechanism and the main memory interface.