JPS5856279A - Address converting system - Google Patents

Abstract

PURPOSE:To realize a free constitution for a memory, by providing plural conversion tables capable of a free conversion of addresses and a conversion table switching means and then switching each conversion table with the switching means to switch a logical address to a real address space. CONSTITUTION:A CPU1 supplies a part of the output logical address bits, e.g., the M bits to each mapper MAP and then the rest N bits to an adder 6 respectively. The selection of each MAP is carried out when the CPU1 rewrites the contents of a register 5. The MAP which is ready for output delivers L bits of the data stored in the storage region corresponding to the M-bit address value to the adder 6 and then supplies the real address to a memory 2 in the form of a data of (L+N) bits. This ensures a free constitution of a memory.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an address conversion method, and more particularly to an address conversion method for allocating addresses output by a processing device to a memory space.

Generally, a processing device (hereinafter referred to as a CP) performs various processes by reading data from a memory, storing data in the memory, and the like. Normally, the address space of the actual memory (real address space) is set to be thicker (1,...
(! It is considered that the PU can perform more processing by using a larger memory space.

In this way, when the real address space is larger than the logical address space, the real address space is allocated to the logical address space in some way. Conventionally, the method described in F below has been used to allocate the real address space. As shown in FIG. 1, there is a method in which memory is arranged in banks and each bank is switched to allocate a real address space. In FIG. 1] is a CP [1 and 2 are memories, and 3 is a bank switching control ff15. As shown in the figure, the memory space of memory 2 is 1°B2. ...B
The memory space is divided into memory spaces of a predetermined capacity called n banks, and one bank is designated by a switching signal from a switching control section. For example, as shown in the same figure, data bits of memory 2 are set to D7 to D.
0 is set to 8 bits, and the address output of 0PUI is set to A7 to A.
Each bank Bl, B2 . ...Bn
will have a storage area represented by 8 bits. Furthermore, the CPU outputs a bank selection signal to the switching control section 3 using signal lines AI1 to A8 of the address bus, for example. The switching control section 3 switches to an appropriate bank based on this bank withdrawal number. After this, OP [A from Jl
The address output via the bus lines D7 to AO is accessed to the address space on the bank selected by the switching control unit, and OP[Jl is a predetermined address on the bank selected via the data bus D7 to DO. Performs data readout and processing.

A second method of real address space allocation is the Matsupa method shown in FIG. In Figure 2, 4 is Matsupar.
A readable and writable memory (RAM) is used. Well, when address data is input to the Matsupar 4, the data previously stored at that address is output. This method uses address output A from OPU 1.
7 - Insert AO into Matsupar-4, C in Matsupar-4
The value stored at the address specified by PU 1 becomes the specified address to memory 2. However, by making the values stored in the storage area of each address of the Matsuper 4 variable, the CPU 1 (/') theory jJ! Addresses can be converted to any real address in memory. In the figure, if the number of bits of input address data of Manper 4 is 8 bits, and the number of pits of output data is 8 bits, the value of logical address (A'7 to AO) and the value of real address (GO0 to D'7) Since there is a one-to-one correspondence between the values of , it is possible to specify only a real address space of the same size as the logical address space represented by 8 bits using mapper 4.

However, every read/write issue from CP II 1 Vw
By specifying the write mode, the contents of the manobar 4 can be rewritten via the data bus Do-D'7. Therefore, by changing the space, the allocation of the real address space to the logical address space can effectively change all the real addresses on the memory 2. Space assignments can be made.

As mentioned above, typical conventional real address space allocation methods include the bank method and the Manova method, but both methods have advantages and disadvantages. In other words, in the bank system, bank switching is easily performed by a switching signal from the CPU, but logical addresses and real addresses are hard-coded, such that the real address of address A in each bank corresponds to a logical address. Fixed on wear. Therefore, there is little flexibility in memory configuration, in other words, in real address allocation. On the other hand, the Matsupa one-sided system requires rewriting the contents of the Matsupa, and has the disadvantage that the operational control of the Matsupa one-sided system becomes complicated.

An object of the present invention is to provide an address conversion method that simultaneously eliminates the drawbacks of both of the above-mentioned methods, allows free allocation of real addresses, and does not require complicated control.

In order to achieve the above object, the address translation method of the present invention includes an address translation unit that makes the output logical address of the processing device correspond to an address in the real address space on the memory, and the address translation unit makes the output logical address of the processing device correspond to the address in the real address space on the memory. In an address conversion method that converts a logical address into a real address within a predetermined address space on memory, the address conversion unit is
'! +ltl consists of a plurality of conversion tables for converting logical addresses into addresses in different real address spaces, and is provided with table switching means, and converts the logical address on the memory using the plurality of conversion tables selected by the table switching means. It is characterized by converting to a real address within a predetermined space.

The present invention will be explained in detail below using Examples.

FIG. 3 is a block diagram showing an embodiment of the address translation method of the present invention. In the figure, 5 is a register and 6 is an adder. In this embodiment, n converters (MAP1) capable of free address conversion shown in FIG.
MAP2. -, MAPn), and each M, AP i register 5 as shown in FIG.
The real address conversion is performed by switching according to the following.

The operation will be explained below.

OP U 1 sends part of the output logical address bits, for example M bits, to each MAP via the address bus, and the remaining IJ
Feeding the bits to adder 6. Here, the selection of the name MAP is carried out by OPU l rewriting the contents of the register 5 -C. In other words, each bit output of the register 5 becomes a selection signal to each MAP.For example, when the bit output is ``1'', the MAP to which that bit output is given becomes ready for output.
The MAP corresponding to the bit output for which the PUI specifies only one bit of each pin in the register 5 as binary ``1'' via the take bus 7 is selected. M is ready for output
The AP inputs the M bits of the logical address output from the CP[J1, and outputs the take stored in the storage area corresponding to the M bit address value to the adder 6. The adder 6 receives, for example, the L-bit Cheetahbi, node output value supplied from the MAP and the N-bit 1 from 0PUI]
A real address is supplied to the memory 2 by using the input value (T,, 1N') as a pit take. The result memory 2 is
The take to be stored at the supplied real address will be output to OP[J1 via the take bus (7).As mentioned above, each λ4A, P is a memory (1(ΔM)) that can be used to store data. OT) [1
, 1 to each MAP are connected to take outputs for data exchange.

It is possible to rewrite the contents of each M A P as necessary.

As described in detail above, according to the present invention, the address converter is configured with a plurality of conversion tables, and each conversion table is capable of data redirection, so that allocation to any real address space can be performed and the memory configuration can be changed. can think freely. Furthermore, since the address assignment can be changed by selecting and switching each conversion table, it is possible to provide an address conversion system with excellent functions such as easy operational control.

[Brief explanation of the drawing]

1 and 2 are diagrams showing a conventionally used address translation method, and FIG. 3 is a block diagram showing an embodiment of the address translation method according to the present invention. l is 02 mouths, 2
is a memory, and 5 is a register. Figure 1 Part Figure Z

Claims (1)

[Claims] an address translation unit that makes the output logical address of the processing device correspond to each address in the real address space on the memory;
In an address conversion method in which the address conversion unit converts a logical address output by a processing device into a real address in a predetermined address space on memory, the address conversion unit converts the logical address into each real address in a different predetermined space. , and a table switching means is provided, and the output logical address of the processing device is assigned to an address in a predetermined real address space on the memory according to the conversion table selected by the table switching means. An address translation method featuring: