JPH0836526A - Information processing system - Google Patents

Abstract

PURPOSE:To speed up the operation at the time of the writing of data to a main memory by a 1st bus master and improve the system performance. CONSTITUTION:When the data are written in the main memory 1, a 1st bus master 2 acquires the right to use only the 1st bus BS1 and sends a write control signal, an address signal, and data to the 1st bus BS1. This system is provided with buffer circuits BF1-BFn which hold the address signal on the 1st bus BS1 in response to the write control signal sent to the 1st bus BS1 and send it to a 2nd bus BS2 at a specific timing together with the write control signal, and a control circuit 5. The 2nd bus masters 3a and 3b invalidate corresponding data in a cache memory 31 according to the write control signal and address signal on the 2nd bus BS2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing system, and more particularly to an information processing system having a plurality of bus masters sharing a main memory.

[0002]

2. Description of the Related Art In an information processing system having a large number of bus masters sharing a main memory, it is electrically and physically difficult to connect all of these bus masters to one bus, and it is the same as the main memory. The bus master connected to this bus requires high-speed operation and is expensive, so the number of bus masters connected to the same bus as the main memory is minimized, and other bus masters are connected at a relatively low speed and are inexpensive. Apart from the above, a method of suppressing the system price is generally adopted by configuring the main memory to be accessed via the bus conversion circuit. A bus master connected to a bus different from the bus to which the main memory is connected has a low speed and accesses the main memory via the two buses and the bus conversion circuit. The overall operation speed will decrease. Therefore, these bus masters usually have a cache memory.

An example of a conventional information processing system of this type is shown in FIG.

This information processing system includes first and second buses BS1 and BS2 for transmitting various signals including data, address signals, and various control signals such as a write control signal and a read control signal, and a first bus. This is the first connection to BS1
The storage data is read from the designated address of this address signal according to the read control signal and the address signal transmitted to the bus of the first bus BS1 and the data transmitted to the designated address of this address signal is read to the first bus BS1 according to the read / write control signal and the address signal. The main memory 1 to be stored and the right to use the first and second buses when the main memory 1 is accessed are acquired and the write control signal, the address signal and the data are sent to the first bus BS1 to the main memory 1. The first bus master 2x for writing the data, sending the read control signal and the address signal, taking in the data read from the main memory 1 and performing a predetermined process;
And a bus conversion circuit 4x for controlling transmission of various signals between the second buses BS1 and BS2, and a cache memory 31. When the cache memory 31 does not store data to be processed, the main memory 1 is accessed. Acquires the right to use the first and second buses BS1 and BS2, sends a read control signal and an address signal to the second bus BS2, fetches the data read from the main memory 1 and stores the data in the cache memory 31. In addition to performing a predetermined process, when a data write to the main memory 1 occurs, a write control signal, an address signal and data are sent to the second bus BS2, and the main memory 1 by another bus master is sent to the second bus. When a write control signal or address signal to the cache is transmitted, the cache corresponding to the specified address of the address signal A plurality of second bus master 3x disabling data memory 31 has a configuration and a 3y.

In this information processing system, when writing of data to the main memory 1 by the first bus master 2x occurs, the first bus master 2x receives the first and second data.
Of the bus BS1 and BS2, the write control signal, the address signal and the data are sent to the first bus BS1. Then, the data is written to the main memory 1, and at the same time, the second bus master 3a is driven by the write control signal and the address signal transmitted from the first bus BS1 to the second bus BS2 via the bus conversion circuit 4x. ，
The corresponding data in the cache memory 31 of 3y is invalidated. In this way, the stored content of the main memory 1 and the stored content of the cache memory 31 can be kept consistent. The acquisition of the right to use the bus of the first bus master 2x is performed by first acquiring the right to use the second bus BS2 and then acquiring the right to use the first bus.

As a method of maintaining the consistency of the stored contents of the main memory 1 and the cache memory 31, there is another method of making the cache memory 31 unusable.

[0007]

In the conventional information processing system described above, when data is written to the main memory 1 by the first bus master 2x, the caches of the main memory 1 and the second bus masters 3a, 3y are cached. In order to keep the data in the memory 31 consistent, the first bus master 2x obtains the right to use the second bus BS2 and then first
The right to use the bus BS1 of the cache memory 31
Invalidate the corresponding data of the
1 has a disadvantage in that it takes a long time to acquire the right to use the bus and cannot operate at high speed, and when the cache memory 31 becomes unusable, the second bus master 3x cannot be used. , 3y have to obtain the first and second buses BS1 and BS2 to access the main memory 1, and therefore cannot similarly operate at high speed, and there is a drawback that the system performance is deteriorated.

An object of the present invention is to provide an information processing system capable of accelerating the operation and improving the system performance when the first bus master writes data to the main memory.

[0009]

An information processing system according to the present invention includes first and second buses for transmitting various signals including data, address signals, and various control signals including write control signals and read control signals. A read control signal connected to the first bus and reading stored data according to a read control signal and an address signal transmitted to the first bus and sending the stored data to the first bus, and a write control signal transmitted to the first bus. , A main memory for writing data according to an address signal and data, and a right to use the first bus when accessing the main memory, and sends a write control signal, an address signal and data to the first bus Then, the data is written to the main memory, and the first
Of various signals between the first and second buses and a first bus master that sends a read control signal and an address signal to the first bus to take in the data transmitted to the first bus and perform a predetermined process. A bus conversion circuit that controls and stops transmission of the various signals when an inhibition signal is transmitted, and a cache memory, and uses the first and second buses when there is no data to be processed in the cache memory Access to the main memory to access the main memory, fetch the data transmitted to the second bus, store the data in the cache memory, perform a predetermined process, and write a control signal to the main memory to the second bus. When the address signal is transmitted, a second bus master which invalidates the data in the cache memory corresponding to the address signal, and a write signal. Becomes an active level, the buffer holds the address signal from the first bus master transmitted to the first bus, and when the read signal becomes an active level, the buffer which transmits the held address signal to the second bus. A circuit, and when a write control signal for the main memory from the first bus master is transmitted to the first bus, the write signal is set to an active level and then the read signal is set to an active level at a predetermined timing. The second bus has a control circuit for transmitting a write control signal for the main memory from the first bus master and the inhibit signal.

Further, a plurality of buffer circuits are provided, and the next write control signal to the main memory by the first bus master when the address signal before transmission to the second bus is held in all of the plurality of buffer circuits. Is transmitted to the first bus, a flash signal is generated from the control circuit, and the flash signal invalidates the data in the cache memory of the second bus master.

[0011]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention.

In this embodiment, first and second buses B for transmitting various signals including data, address signals, and various control signals including write control signals and read control signals.
S1 and BS2 are connected to the first bus BS1, and stored data is read out according to the read control signal and the address signal transmitted to the first bus BS and sent to the first bus BS1 to be sent to the first bus BS1. The transmitted write control signal,
A main memory 1 for writing data according to an address signal and data, and a right to use the first bus BS when accessing the main memory 1 to obtain a write control signal, an address signal and data on the first bus BS1. To write data to the main memory 1,
A first bus master 2 which sends a read control signal and an address signal to the first bus BS1 to take in the data transmitted to the first bus BS1 and performs a predetermined process;
The bus conversion circuit 4 controls the transmission of various signals between the buses BS1 and BS2 and stops the transmission of the various signals when the inhibition signal INH is transmitted, and the cache memory 31 is provided. When there is no data, the right to use the first and second buses BS1 and BS2 is acquired, the main memory is accessed, the data transmitted to the second bus BS2 is stored in the cache memory 31, and predetermined processing is performed. When the write control signal and the address signal for the main memory 1 are transmitted to the second bus BS2, the data in the cache memory 31 corresponding to this address signal is invalidated, and the flash signal FLSH is transmitted to the second bus. Then, the second bus masters 3a and 3b for invalidating the cache memory 31, and
When the corresponding write signal (WE1 to WEn) becomes the active level, the address signal from the first bus master 2 transmitted to the first bus BS1 is held, and when the corresponding read signal (OE1 to OEn) becomes the active level. A plurality of buffer circuits BF1 to BFn for transmitting the held address signal to the second bus BS2, and the first bus B
When a write control signal for the main memory 1 from the first bus master 2 is transmitted to S1, write signals WE1 to W
After one of the En signals is set to the active level, a predetermined read signal of the read signals OE1 to OEn is set to the active level at a predetermined timing and the second bus B
The write control signal for the main memory 1 from the first bus master 2 and the inhibit signal INH are transmitted to S2, and the second bus BS2 is supplied to all of the plurality of buffer circuits BF1 to BFn.
When the address signal before transmission to the
And a control circuit 5 for generating a flash signal FLSH and transmitting it to the second bus BS2 when the next write control signal for the main memory 1 by the bus master 2 is transmitted to the first bus BS1. .

Next, the operation of this embodiment will be described focusing on the operation when data is written in the main memory 1 by the first bus master 2.

Main memory 1 by first bus master 2
When the data is written in, the control circuit 5 recognizes the write control signal for the main memory 1 on the first bus BS1 transmitted from the first bus master 2, and first activates the write signal WE1. Level. In response to the active level of the write signal WE1, the buffer circuit B
F1 takes in and holds the address signal ADi on the first bus BS1 transmitted from the first bus master 2.

After that, the control circuit 5 controls the main memory 1 on the first bus BS1 transmitted from the first bus master 2.
The write control signal to the second bus BS2 is transmitted to the second bus BS2, the read signal OE1 is set to the active level, and the inhibit signal INH is generated and sent to the second bus. In response to the active level of the read signal OE1, the buffer circuit BF1 sends the held address signal to the second bus BS2. The second bus masters 3a and 3b recognize the write control signal to the main memory 1 by the first bus master 2 transmitted to the second bus BS2, and the first bus master 2 transmitted to the second bus BS2. The write control signal to the main memory 1 by the second bus BS.
2 invalidates the data of the cache memory 31 corresponding to the address signal ADo from the buffer circuit BF1 transmitted to the memory 2. On the other hand, the bus conversion circuit 4 stops the transmission of various signals between the first and second buses BS1 and BS2 in response to the inhibition signal INH, and stabilizes the operation of each unit.

In this way, the first bus master 2 acquires the right to use the first bus BS1 and sends the write control signal, the address signal, and the data to the main memory 1 to the first bus BS to perform the main operation. Data can be written in the memory 1, and the control circuit 5 and the buffer circuits BF1 to B
Fn allows the cache memory 3 of the second bus masters 3a and 3b to be written in parallel with the writing of data to the main memory 1.
Since the data corresponding to 1 can be invalidated, the operation can be speeded up. Further, since data other than the corresponding data in the cache memory 31 is valid,
Processing based on these data is possible, and in this case as well, high-speed operation can be performed and system performance can be improved.

However, the writing of data to the main memory 1 by the first bus master 2 and the buffer circuits BF1 to BF1.
Address signal ADo from BFn to the second bus BS2
Is asynchronous with the transmission of the address signal ADo to the second bus BS2, and even after the address signal ADo is transmitted to the second bus BS2, the first bus master 2 writes data to the main memory 1 one after another even if it is cleared. Is continuously performed, the first bus master 2 holds and holds the address signal ADi from the first bus BS1 into the buffer circuits BF1 to BFn.
Of the buffer circuit BF1 because it is synchronized with the write operation of
There may be a case where the address signal before being transmitted to the second bus BS2 is held in all of to BFn. If the first bus master 2 writes to the main memory 1 at such a time, the data is The consistency of can not be maintained. Therefore, the control circuit 5 generates the flash signal FLSH to invalidate the data in the cache memory 31 of the second bus masters 3a and 3b.

[0019]

As described above, according to the present invention, when data is written in the main memory by the first bus master,
The first bus master acquires the right to use only the first bus, sends a write control signal to the main memory, an address signal, and data to the first bus to write data to the main memory. The invalidation of the corresponding data in the cache memory of the second bus master is performed by holding the address signal from the first bus master transmitted to the first bus in the buffer circuit and asynchronously with the writing of the data to the main memory. By adopting a configuration that is performed in parallel, it is not necessary to acquire the right to use the second bus by the first bus master as in the conventional example, so that the time can be shortened and the writing of data to the main memory is possible. Since the corresponding data in the cache memory and the invalidation of the corresponding data in the cache memory are performed in parallel, the operation can be speeded up, and the cache circuit is filled until the buffer circuit overflows. Since other than the above corresponding data Shumemori is effective there is an effect that it is possible to improve the speed and performance of the system operation.

[Brief description of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a block diagram showing an example of a conventional information processing system.

[Explanation of symbols]

 1 main memory 2, 2x, 3a, 3b, 3x, 3y bus master 4, 4x bus conversion circuit 5 control circuit 31 cache memory BF1 to BFn buffer circuit BS1, BS2 bus

Claims (3)

[Claims] 1. A first bus and a second bus for transmitting various signals including data, an address signal, and various control signals including a write control signal and a read control signal, and the first bus connected to the first bus. Main memory for reading the stored data according to the read control signal and the address signal transmitted to the first bus and sending it to the first bus and writing the data according to the write control signal, the address signal and the data transmitted to the first bus. When the memory and the main memory are accessed, the right to use the first bus is acquired and the first right is acquired.
The write control signal, the address signal and the data are sent to the bus to write the data to the main memory, and the read control signal and the address signal are sent to the first bus to be transmitted to the first bus. A bus conversion that controls the transmission of various signals between the first bus master that takes in the specified data and performs a predetermined process and the first and second buses and that stops the transmission of the various signals when the inhibition signal is transmitted. A circuit and a cache memory are provided, and when there is no data to be processed in the cache memory, the first and second
To obtain access to the main memory to access the main memory, fetch the data transmitted to the second bus, store the data in the cache memory, perform a predetermined process, and set the second bus to the main memory. Secondly, when the write control signal and the address signal are transmitted, the data in the cache memory corresponding to the address signal is invalidated.
And the address signal from the first bus master transmitted to the first bus when the write signal goes to the active level and the held address signal when the read signal goes to the active level. And a read circuit at a predetermined timing after the write signal is set to an active level when a write control signal from the first bus master to the main memory is transmitted to the first bus. Is set to an active level and the first bus is connected to the second bus.
An information processing system, comprising: a control circuit for transmitting a write control signal from the bus master to the main memory and the inhibit signal. 2. A next write control signal to the main memory by the first bus master when a plurality of buffer circuits are provided and the address signals before transmission to the second bus are held in all of the plurality of buffer circuits. 2. The information processing system according to claim 1, wherein a flash signal is generated from the control circuit when is transmitted to the first bus, and the flash signal invalidates the data in the cache memory of the second bus master. 3. A plurality of buffer circuits are provided, and when the addresses stored in these plurality of buffer circuits are transmitted to the second bus, the buffer circuits are set in an empty state so that the next address signal can be held. The information processing system according to claim 1.