JPH10154115A - Information processor provided with lan controller having cache - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a LAN controller from generating underrun and overrun in an information processor which is provided with the LAN controller. SOLUTION: When a LAN controller 2 receives receiving data for its own device via a LAN 11, the controller 2 writes it on a LAN cache 3. The receiving data written on the cache 3 is written in a receiving data area 1R in main memory 1 by a LAN memory controller 4, further written on CPU cache 6 by a memory controller 7 and read by a CPU 5. Transmitting data which is transmitted by the CPU 5 it written in a transmission data area 1S in the memory 1 by the controller 7, the controller 4 writes the transmission data stored in the area 18 on the cache 3, and the controller 2 sends the transmission data written on the cache 3 to the LAN 11.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an information processing apparatus having a LAN controller for transmitting and receiving data via a LAN, and more particularly to an information processing apparatus having a cache-equipped LAN controller having a cache.

[0002]

2. Description of the Related Art Conventionally, while receiving received data addressed to the own device transmitted via a LAN, the transmitted data is
In an information processing apparatus having a LAN controller for sending data to an AN, the LAN controller is connected to an I / O bus, and data is exchanged with a main memory via the I / O bus. Was common. That is,
At the time of data reception, the received data is written to the reception data area in the main memory via the I / O bus. At the time of data transmission, the transmission data stored in the transmission data area of the main memory is written to the I / O bus. Through the lead. The reception data written in the reception data area of the main memory is read by the CPU, and the transmission data in the transmission data area is
It was written by U.

[0003]

As described above, in an information processing apparatus having a conventional LAN controller, the LAN controller is connected to the I / O bus and the I / O bus is connected to the I / O bus.
Since data is exchanged with the main memory via the bus, there is a problem that an underrun or overrun occurs in a LAN controller that requests the bus in real time. The reason is I
In a configuration in which a LAN controller is connected to the / O bus,
This is because it is necessary to use the I / O bus in a time-sharing manner with a plurality of I / O controllers connected in parallel to the / O bus and not requiring real-time processing and the LAN controller.

Japanese Patent Application Laid-Open Nos. 4-100164 and 4-321145 disclose that a cache memory (cache) is provided in a CPU to increase the processing speed of data between a main memory and the CPU. However, the above problem cannot be solved only by providing a cache in the CPU.

It is an object of the present invention to provide an information processing apparatus having a LAN controller with a cache which can prevent an underrun or an overrun from occurring in a LAN controller.

[0006]

According to the present invention, a main memory having a reception data area and a transmission data area, and a copy of the reception data area and a copy of the transmission data area in the main memory are stored. And the received data received via the LAN
A LAN controller that writes data to the AN cache, reads transmission data to be transmitted via the LAN from the LAN cache, and sends the data to the LAN, and a dedicated reception data written to the LAN cache by the LAN controller. The transmission data stored in the transmission data area is written to the reception data area using a bus, and the transmission data stored in the transmission data area is written to the LA using a dedicated bus.
A LAN memory controller is provided for maintaining data consistency between the LAN cache and the reception data area and transmission data area of the main memory by writing to the N cache.

In this configuration, a LAN controller writes received data to a LAN cache,
The memory controller writes the received data written in the LAN cache to the received data area of the main memory using a dedicated bus. At the time of data transmission, the LAN memory controller writes the transmission data stored in the transmission data area of the main memory to the LAN cache via a dedicated bus, and the LAN controller writes the transmission data to the LAN cache. The transmitted data is transmitted to the LAN.

The present invention further provides a CPU cache in which a copy of the reception data area and a copy of the transmission data area are stored so as to enable high-speed data processing between the CPU and the main memory. A CPU for writing transmission data to the CPU cache and reading reception data stored in the CPU cache;
U, the transmission data written to the CPU cache is written to the transmission data area using a dedicated bus, and the reception data stored in the reception data area is written to the CPU using a dedicated bus. A memory controller is provided for maintaining data consistency between the CPU cache and the reception data area and transmission data area of the main memory by writing to the cache.

In this configuration, when data is transmitted, C
The PU writes transmission data to the CPU cache, and the memory controller writes the transmission data written to the CPU cache to the transmission data area of the main memory using a dedicated bus. At the time of data reception, the memory controller writes the reception data stored in the reception data area of the main memory to the CPU cache using a dedicated bus, and the CPU writes the reception data written to the CPU cache. Read data.

[0010]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, in which a main memory 1, a LAN controller 2, and an LA
N cache 3, LAN memory controller 4, C
PU 5, CPU cache 6, memory controller 7, I / O bus controller 8, I / O bus 9,
A plurality of I / O controllers 10-1 to 10-n;
N11, buses 12 to 17, and a signal line 18 are included.

The main memory 1 includes a reception data area 1R for storing reception data and a transmission data area 1S for storing transmission data.

The LAN controller 2 is connected to a LAN 11 and a LAN cache 3 dedicated to the LAN controller via a bus 12 dedicated to the LAN controller. The LAN cache 3 stores a copy of the reception data area 1R and the transmission data area 1S in the main memory 1. The LAN controller 2 writes the reception data received via the LAN 11 to the LAN cache 3, and writes the received data to the LAN cache 3. 3 is transmitted to the LAN 11.

The LAN cache 3 is connected to the main memory 1 via buses 13 and 14 dedicated to the LAN controller and the LAN memory controller 4, and the LAN memory controller 4 maintains data consistency with the main memory 1. .

The CPU 5 is connected to the CPU cache 6 via a bus 15 dedicated to the CPU.
Are connected to the main memory 1 via buses 16 and 17 dedicated to the CPU and the memory controller 7. CPU
The data consistency between the cache 6 and the main memory 1 is maintained by the memory controller 7.

A plurality of I / O controllers 10-1 to 10-n are connected to the I / O bus 9 in parallel.
The / O controllers 10-1 to 10-n are connected to the memory controller 7 by the I / O bus controller 8.

The LAN memory controller 4 and the memory controller 7 are connected via a dedicated signal line 18. In order to maintain data consistency between the main memory 1, the LAN cache 3 and the CPU cache 6, Line 1
8 to notify the other party that the LAN cache 3 and the CPU cache 6 have been replaced, and issue a write-back instruction to the other party.

FIG. 2 is a diagram showing the operation of the LAN memory controller 4 and the memory controller 7 when receiving data.
Is a diagram showing the operation of the LAN memory controller 4 and the memory controller 7 at the time of data transmission. The operation of this embodiment will be described below with reference to the drawings.

First, the operation at the time of data reception will be described.

When the LAN controller 2 receives the received data addressed to the own device transmitted via the LAN 11, it writes the received data to the LAN cache 3. At this time, if a copy of the received data area 1R exists in the LAN cache 3, it is replaced with the received data.

Upon detecting that the received data has been written to the LAN cache 3, the LAN memory controller 4 notifies the memory controller 7 via the signal line 18 that the LAN cache 3 has been replaced (FIG. 2). reference). Incidentally, the fact that the received data has been written to the LAN cache 3 means that, for example, the LAN controller 2 notifies the LAN memory controller 4 that the received data has been written, or when the received data is written. It can be detected by checking the write signal and write address output from the LAN controller 2.

When notified by the LAN memory controller 4 that the LAN cache 3 has been replaced, the memory controller 7 invalidates the copy of the received data area 1R in the CPU cache 6, if any. . That is, the reception data stored as a copy of the reception data area 1R in the LAN cache 3 and the CPU
Since there is a possibility that the copy of the reception data area 1R stored in the cache 6 may be different, the memory controller 7 invalidates the copy of the reception data area 1R stored in the CPU cache 6. .

Thereafter, when the CPU 5 needs the received data, the CPU 5 tries to read a copy of the received data area 1R stored in the CPU cache 6. However, a copy of the reception data area 1R does not exist in the CPU cache 6, or even if it exists, it is invalidated, so that a miss hit occurs. If a mishit occurs, the memory controller 7 issues a write-back instruction to the LAN memory controller 4 via the signal line 18 because the LAN memory controller 4 is notified that the LAN cache 3 has been replaced. I do. That is, the content of the reception data area 1R of the main memory 1 and L
Since the copy of the received data area 1R in the AN cache 3 does not match, a write-back command is issued to the LAN memory controller 4 in order to match the two.

Upon receiving the write-back instruction, the LAN memory controller 4 writes the received data stored in the LAN cache 3 back to the received data area 1R of the main memory 1 using the buses 13 and 14, and writes the data. When the back is completed, the memory controller 7 is notified of the completion via the signal line 18.

Upon receiving this notification, the memory controller 7 reads the received data from the received data area 1R of the main memory 1 and replaces it in the CPU cache 6,
The CPU 5 reads the replaced received data.

Next, the operation for transmitting data via the LAN 11 will be described.

When the CPU 5 generates transmission data, the CPU 5 writes the transmission data to the CPU cache 6.

When detecting that the transmission data has been written to the CPU cache 6, the memory controller 7 notifies the LAN memory controller 4 via the signal line 18 that the replacement of the CPU cache 6 has been performed ( (See FIG. 3). The writing of the transmission data to the CPU cache 6 can be detected in the same manner as the case where the reception data is written to the LAN cache 3.

Upon receiving this notification, the LAN memory controller 4 stores the transmission data area 1 in the LAN cache 3.
If a copy of S exists, the copy is invalidated.

Thereafter, the LAN controller 2 performs a read operation on the LAN cache 3 to transmit the transmission data stored in the LAN cache 3. However, since a copy of the transmission data area 1S does not exist in the LAN cache 3, or even if it exists, it is invalidated, so that a miss hit occurs.

When a miss occurs, the LAN memory controller 4 issues a write-back instruction to the memory controller 7 because the memory controller 7 is notified that the CPU cache 6 has been replaced. That is, since the contents of the transmission data area 1S of the main memory 1 and the copy of the transmission data area 1S stored in the CPU cache 6 do not match, a write-back command is issued to the memory controller 7 in order to match them. Issue

As a result, the memory controller 7
The transmission data stored in the PU cache 6 is written back to the transmission data area 1S of the main memory 1, and when the write back is completed, the fact is notified to the LAN memory controller 4 via the signal line 18.

When receiving this notification, the LAN memory controller 4 replaces the contents of the transmission data area 1S in the LAN cache 3, and the LAN controller 2 reads the replaced transmission data and sends it to the LAN 11.

Next, the I / O controller 10-j (1 ≦
j ≦ n), the case where data is written to the main memory 1 will be described.

When data to be written to the main memory 1 is generated in the I / O controller 10-j, the I / O controller
After obtaining the right to use the I / O bus 9, the O controller 10-j writes the write data, the write address,
Outputs a write signal.

These are transferred to the memory controller 7 via the I / O bus controller 8. In the memory controller 7, if the data of the write address is stored in the CPU cache 6, the CPU cache 6 and the main memory 1 are rewritten.
Notifying the AN memory controller 4 that the main memory 1 has been rewritten, and if not stored, rewriting only the main memory 1 and rewriting the main memory 1 to the LAN controller 4 Notify. Upon receiving this notification, the LAN controller 4 sets the data corresponding to the rewritten data to L.
If it is stored in the AN cache 3, the LAN cache 3 is replaced.

Next, the operation of the I / O controller 10-j when it becomes necessary to read data from the main memory 1 will be described.

When it becomes necessary to read data from the main memory 1, the I / O controller 10-j
After the right to use the / O bus 9 is obtained, a read address and a read signal are output to the I / O bus 9.

These are transferred to the memory controller 7 via the I / O bus controller 8. In the memory controller 7, the data of the passed read address is stored in the CPU.
If the data has been rewritten in the cache 6, the CPU cache 6 is flushed.
Data is read from the main memory 1 in accordance with the read address passed from the / O bus controller 8, and the read data is passed to the I / O controller 10-j via the I / O bus controller 8 and the I / O bus 9. If the data of the passed read address has been rewritten in the LAN cache 3, a write-back instruction is issued to the LAN memory controller 4, and the LA
After the N cache 3 has been discharged, the data stored in the read address is transferred via the I / O controller 8 and the I / O bus 9.

[0040]

As described above, according to the present invention,
In the LAN controller, real-time data processing can be performed, so that underrun or overrun does not occur. The reason is that the LAN controller has a dedicated LAN cache and a LAN memory controller that uses a dedicated bus to maintain data consistency between the LAN cache and the main memory. This is because the idle waiting time of the / O bus becomes unnecessary.

Further, in the present invention, the CPU is also a dedicated CPU.
Since the cache is provided, the speed of data transmission / reception via the LAN can be further increased.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 shows the LAN memory controller 4 when receiving data.
FIG. 4 is a diagram for explaining the operation of the memory controller 7;

FIG. 3 shows the LAN memory controller 4 during data transmission.
FIG. 4 is a diagram for explaining the operation of the memory controller 7;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Main memory 1R ... Reception data area 1S ... Transmission data area 2 ... LAN controller 3 ... LAN cache 4 ... LAN memory controller 5 ... CPU 6 ... CPU cache 7 ... Memory controller 8 ... I / O bus controller 9 ... I / O Buses 10-1 to 10-n: I / O controller 11: LAN 12 to 17: Bus 18: Signal line

Claims (3)

[Claims] 1. A main memory having a reception data area and a transmission data area, a LAN cache storing a copy of the reception data area and a copy of the transmission data area in the main memory, and reception data received via the LAN. A LAN controller that writes transmission data to be transmitted through the LAN from the LAN cache and sends the data to the LAN while writing the transmission data transmitted through the LAN to the LAN cache. A dedicated bus is used to write to the reception data area, and the transmission data stored in the transmission data area is written to the L using a dedicated bus.
An LA with a cache, comprising: a LAN memory controller that maintains data consistency between the LAN cache and a reception data area and a transmission data area of the main memory by writing to an AN cache.
An information processing device including an N controller. 2. A CPU cache in which a copy of the reception data area and a copy of the transmission data area are stored, and a CPU which writes transmission data in the CPU cache and reads reception data stored in the CPU cache. Writing the transmission data written to the CPU cache by the CPU to the transmission data area using a dedicated bus, and transmitting the reception data stored in the reception data area using the dedicated bus. 2. The cache according to claim 1, further comprising a memory controller that writes data to the CPU cache to maintain data consistency between the CPU cache and a reception data area and a transmission data area of the main memory. Information processing device provided with a LAN controller. 3. An I / O bus and a plurality of I / O controllers connected to the I / O bus and accessing the main memory via the I / O bus. Item 2. An information processing apparatus comprising the LAN controller with a cache according to Item 2.