JPS5713562A - Control system of external memory - Google Patents

Control system of external memory

Info

Publication number
JPS5713562A
JPS5713562A JP8652280A JP8652280A JPS5713562A JP S5713562 A JPS5713562 A JP S5713562A JP 8652280 A JP8652280 A JP 8652280A JP 8652280 A JP8652280 A JP 8652280A JP S5713562 A JPS5713562 A JP S5713562A
Authority
JP
Japan
Prior art keywords
memory
data
address space
transfers
mode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8652280A
Other languages
Japanese (ja)
Inventor
Yoshiyuki Kobayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP8652280A priority Critical patent/JPS5713562A/en
Publication of JPS5713562A publication Critical patent/JPS5713562A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Abstract

PURPOSE:To elevate a throughout of a system, by inserting a buffer memory between a main memory and an external memory as necessary, and also using the buffer memory as an address space of the main memory. CONSTITUTION:Between a main memory 50 and an external memory 10 is provided a mode which transfers a data without making it pass through a buffer memory 70. Moreover, this system is provided with a mode which transfers a data between the memory 50 and the memory 70 if a necessary data is stored in the memory 70, and transfers a data between the memory 50 and the memory 10 unless a necessary data is stored in the memory 70. Furthermore, an address space of the memory 50 is extended to an address space of the memory 70, the address space of the memory 50 and the memory 70 is made one physical address space, and it is shifted to a mode in which a CPU60 uses a data in these memories by a word each. In this way, a data is transferred at a high speed, a countermeasure is taken for a fault of the memory 70, and capacity of the memory 50 is increased equivalently.
JP8652280A 1980-06-27 1980-06-27 Control system of external memory Pending JPS5713562A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8652280A JPS5713562A (en) 1980-06-27 1980-06-27 Control system of external memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8652280A JPS5713562A (en) 1980-06-27 1980-06-27 Control system of external memory

Publications (1)

Publication Number Publication Date
JPS5713562A true JPS5713562A (en) 1982-01-23

Family

ID=13889314

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8652280A Pending JPS5713562A (en) 1980-06-27 1980-06-27 Control system of external memory

Country Status (1)

Country Link
JP (1) JPS5713562A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58186867A (en) * 1982-04-27 1983-10-31 Hitachi Ltd Disk cache control system
JPS5960552A (en) * 1982-09-27 1984-04-06 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Peripheral data memory system
JPS5969855A (en) * 1982-10-14 1984-04-20 Yokogawa Hokushin Electric Corp High speed accessing method of disc data
JPH02231621A (en) * 1989-03-06 1990-09-13 Hitachi Ltd Information transfer system for rotary memory device
JPH02234251A (en) * 1989-03-08 1990-09-17 Nec Corp Control system for extended storage

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58186867A (en) * 1982-04-27 1983-10-31 Hitachi Ltd Disk cache control system
JPH0312743B2 (en) * 1982-04-27 1991-02-20 Hitachi Ltd
JPS5960552A (en) * 1982-09-27 1984-04-06 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Peripheral data memory system
JPS5969855A (en) * 1982-10-14 1984-04-20 Yokogawa Hokushin Electric Corp High speed accessing method of disc data
JPH02231621A (en) * 1989-03-06 1990-09-13 Hitachi Ltd Information transfer system for rotary memory device
JPH02234251A (en) * 1989-03-08 1990-09-17 Nec Corp Control system for extended storage

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