JPS52105740A - Buffer memory fead-out control system - Google Patents

Buffer memory fead-out control system

Info

Publication number
JPS52105740A
JPS52105740A JP2250476A JP2250476A JPS52105740A JP S52105740 A JPS52105740 A JP S52105740A JP 2250476 A JP2250476 A JP 2250476A JP 2250476 A JP2250476 A JP 2250476A JP S52105740 A JPS52105740 A JP S52105740A
Authority
JP
Japan
Prior art keywords
fead
control system
buffer memory
out control
reading
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2250476A
Other languages
Japanese (ja)
Other versions
JPS573971B2 (en
Inventor
Hideo Kuroda
Hiroshi Yasuda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP2250476A priority Critical patent/JPS52105740A/en
Publication of JPS52105740A publication Critical patent/JPS52105740A/en
Publication of JPS573971B2 publication Critical patent/JPS573971B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Storing Facsimile Image Data (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)

Abstract

PURPOSE: To lower the maximal bit processing speed, by storing variable length codes as they are, and reading them through a parallel processing.
COPYRIGHT: (C)1977,JPO&Japio
JP2250476A 1976-03-01 1976-03-01 Buffer memory fead-out control system Granted JPS52105740A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2250476A JPS52105740A (en) 1976-03-01 1976-03-01 Buffer memory fead-out control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2250476A JPS52105740A (en) 1976-03-01 1976-03-01 Buffer memory fead-out control system

Publications (2)

Publication Number Publication Date
JPS52105740A true JPS52105740A (en) 1977-09-05
JPS573971B2 JPS573971B2 (en) 1982-01-23

Family

ID=12084564

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2250476A Granted JPS52105740A (en) 1976-03-01 1976-03-01 Buffer memory fead-out control system

Country Status (1)

Country Link
JP (1) JPS52105740A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS594255A (en) * 1982-06-30 1984-01-11 Fujitsu Ltd Code converting circuit to variable length code
JPS6195624A (en) * 1984-10-12 1986-05-14 ジーメンス・アクチエンゲゼルシヤフト Code word converter
JPS62157424A (en) * 1985-12-18 1987-07-13 アドバンスト・マイクロ・デイバイシズ・インコ−ポレ−テツド Apparatus for converting asynchronous different type variable width parallel data pattern input signals into series data pattern signals
US5309156A (en) * 1991-02-13 1994-05-03 Fujitsu Limited Variable-length code decoding device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5178946A (en) * 1974-12-30 1976-07-09 Nippon Telegraph & Telephone BATSUFUAMEMORYO MIDASHI HOSHIKI

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5178946A (en) * 1974-12-30 1976-07-09 Nippon Telegraph & Telephone BATSUFUAMEMORYO MIDASHI HOSHIKI

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS594255A (en) * 1982-06-30 1984-01-11 Fujitsu Ltd Code converting circuit to variable length code
JPH0379889B2 (en) * 1982-06-30 1991-12-20 Fujitsu Kk
JPS6195624A (en) * 1984-10-12 1986-05-14 ジーメンス・アクチエンゲゼルシヤフト Code word converter
JPS62157424A (en) * 1985-12-18 1987-07-13 アドバンスト・マイクロ・デイバイシズ・インコ−ポレ−テツド Apparatus for converting asynchronous different type variable width parallel data pattern input signals into series data pattern signals
US5309156A (en) * 1991-02-13 1994-05-03 Fujitsu Limited Variable-length code decoding device

Also Published As

Publication number Publication date
JPS573971B2 (en) 1982-01-23

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