JPS594255A - Code converting circuit to variable length code - Google Patents

Abstract

PURPOSE:To process a variable length code having larger word length than that of an output data, by providing a pre-processing circuit splitting inputted a variable length code data into plural data having a prescribed word length or below. CONSTITUTION:A code converting circuit consists of the pre-processing circuit 2 and a code converting section 3. A variable length code and the code length information having n0 of the maximum number of bits are inputted to the preprocessing circuit 2, and the variable length code is split into the variable length code having the maximum bit number n1(n1<n0). When n0=16, n1=8, the 15-bit code length information and the code pattern information are read in FFs 21, 22, the code length information is converted into the code length information of higher-order 8-bit and lower-order 7-bit at a code length converting circuit 23 and outputted in parallel. The code pattern information is outputted in the order of the higher-order 8-bit and the lower-order 7-bit with a selecting signal of a control circuit 28 with a selecting circuit 24. In synchronizing with it, the code length information is selected at a selecting circuit 25 and outputted. Thus, the two sets of split information are read sequentially in FFs 26, 27 by doubled clock signals and applied to a code converting section 3. The function of the converting section is the same as that of a conventional system.

Description

Detailed Description of the Invention (1) Technical Field of the Invention The present invention relates to a code conversion circuit for variable length codes, and in particular converts variable length code data input in parallel into codes of a predetermined word length or less in a preprocessing circuit. The present invention relates to a code conversion circuit for dividing variable length codes.

(2) Background of the technology Generally, in information transmission, variable-length codes are used, in which the number of bits in one word changes depending on the content of the information, and fixed-length codes, in which the number of bits in one word are always constant. It is being The variable length code system has the advantage that the total number of bits required to transmit the same amount of information can be reduced compared to the fixed length code system, and is used for transmitting image signals, audio signals, etc. However, since the number of bits differs from word to word, it is inconvenient to process the words as they are, and the circuit becomes complicated. Such drawbacks can be eliminated by converting a signal string consisting of codes of increasing length into parallel data divided into parts of a fixed number of bits. Against this background, it is desired to realize a circuit that converts variable length codes to fixed length codes.

(3) Prior Art and Problems A code conversion circuit for a conventional variable length code is shown in FIG. The code conversion circuit 1 shown in FIG.
I2, song, and D engineering are input in parallel, and code length information BN is used to indicate the number of bits of the input variable length code.
1. BN 2...BNm is input. In the code conversion circuit 1, the input variable-length code data is converted into output data DOI of n-bit fixed-length code.
, DO2... is output as DOW.

The above-mentioned operation of the code conversion circuit 1 shown in FIG. 1 will be explained using the input/output data example shown in FIG. For example, input data (A) in Fig. 2, (
B), (C)...(F) are sequentially connected to the code conversion circuit 1.
Suppose that it is input to . Since the first input data (A) has 6 pits, the first 2 bits of the next input data (B) are added to the tail, resulting in 8-bit output data (A').
is output as Next, 1 of the remaining input data (B)
The first 7 bits of the next input data (C) are added to the bits and output as 8-bit output data (B'). Next, all 4 bits of the next input data (D) are added to the remaining 1 bit of the input data (C), and the first 3 bits of the next input data (E) are added to the remaining 1 bit of the 8-bit data. It is output as output data (C'). Further, all 6 bits of the next data (F) are added to the remaining 2 bits of data (E) and output as output data (D').

The operation of the code conversion circuit shown in FIG. 1 is realized, for example, by a circuit disclosed in Japanese Patent Application No. 55-017,259. By the way, in the code conversion circuit shown in Fig. 1,
Since the maximum word length to be processed is n bits, if the number of points of input data is large, it is necessary to increase the number of input data, which increases the complexity of the circuit configuration and the size of the device. There is a problem.

(4) Object of the Invention In view of the problems of the conventional type described above, the main object of the invention is to provide the processing circuit capable of dividing input variable-length code data into a plurality of data having a predetermined word length or less. By providing this, it is possible to process a variable length code having a word length larger than the word length of the output data, and input data with a large word length can be processed by a device with a relatively small circuit scale. An object of the present invention is to provide a code conversion circuit for variable length codes.

(5) Structure of the Invention In the present invention, variable-length code input data having a length of 9 words or less is input in parallel and is converted into fixed-length code output data having a length of 9 words. A variable method characterized in that a preprocessing circuit is provided to divide a code of length or more into a plurality of codes of length or less, and the code converter is operated at a speed proportional to the number of divisions. A code conversion circuit for long codes is provided.

(6) Embodiment of the Invention A code conversion circuit for variable length codes as an embodiment of the present invention is shown in FIG. The code conversion circuit for the variable length code shown in FIG. 3 is composed of a preprocessing circuit 2 and a code conversion section 3. An example of the configuration of the preprocessing circuit shown in FIG. 3 is shown in FIG.

In the code conversion circuit shown in FIG. 3, the preprocessing circuit 2 has a maximum number of bits. variable length code pattern information and code length information are input. In the preprocessing circuit 2, the input variable length code has a maximum number of bits n, (n, (n, )
variable-length codes. For example, le. =15. n,
= 8, when the input data is a 15-bit code, it is divided into two codes, 8 bits and 7 bits, in the preprocessing circuit 2, and code length information representing 8 bits and 7 bits is attached to each code. and is supplied to the code conversion section 3.

In this case, two pieces of data are supplied to the code converter 3 for each input data and processed. The code conversion unit 3 has the same function as the code conversion circuit 1 shown in FIG.
7,259.

The functions of the preprocessing circuit 2 described above are realized, for example, by the circuit configuration shown in FIG. The preprocessing circuit 2 in FIG.
Flip-flop circuit 21 to which input code length information is input
, a flip-flop circuit 22 to which input code pattern information is input, a circuit 23 for converting input code length information into code length information for divided codes, and a selection for selectively outputting code patterns divided from input code pattern information. circuit 24, a selection circuit 25 that selectively outputs code length information of divided codes, a flip-flop circuit 26 that outputs code length information of divided codes, a flip-flop circuit 27 that outputs divided code pattern information, It also has a control circuit 28 that controls each of the circuits described above.

In the case of the above example, code length information and code pattern information of 15 pints are read into flip-flop circuits 21 and 22, respectively, by a clock signal. The read code length information is converted into two pieces of code length information, ie, upper 8 bits and lower 7 bits, in a code length conversion circuit 23, and outputted in parallel.

On the other hand, in the selection circuit 24, the upper 8 bits of the code pattern information are outputted first, and then the lower 7 bits are outputted, according to a selection signal from the control circuit 28. In synchronization with this, the selection circuit 25 also selects 8-bit code length information first, and then selects and outputs 7-bit code length information.

In this way, code length information and code pattern information for the two divided codes are transmitted from the control circuit 28.
Flip-flop circuit 26 sequentially by double clock signal
and 27 and supplied to the code conversion section 3.

Therefore, in the code conversion circuit shown in FIG. 3, it is possible to process variable length codes of maximum 16 bits in the code conversion circuit having an 8-pit configuration. Of course, by increasing the number of divisions in the preprocessing circuit 2, it is also possible to process variable length codes of 16 pinto or more.

(7) Effects of the Invention According to the present invention, by dividing a variable length code having a relatively large word length into a plurality of codes having word lengths equal to or less than a predetermined word length, the word length of the input code is A code conversion circuit that can convert a variable length code to a fixed length code using a smaller circuit than a circuit that processes the code as is can be provided.

[Brief explanation of the drawing]

mm1 is a circuit diagram of a code conversion circuit for a conventional variable length code, FIG. 2 is a diagram explaining the operation of the circuit of FIG. 1, and FIG. 3 is a circuit diagram of a code conversion circuit for a conventional variable length code. Circuit Diagram of Code Conversion Circuit for Codes FIG. 4 is a circuit diagram of a configuration example of the preprocessing circuit in FIG. 3. (Description of symbols) 1: code conversion circuit, 2: preprocessing circuit, 3: code conversion unit, 21.22, 26, 27: flip-flop circuit,
23: code length conversion circuit; 24, 25: selection circuit; 282: control circuit. Patent applicant: Fujitsu Corporation Nippon Telegraph and Telephone Corporation Patent agent: Akira Aoki, patent attorney: Kazuyuki Nishidate, patent attorney: 1) Yukio, patent attorney: Akira Yamaguchi

Claims (1)

[Claims] Variable-length code input data with word length or less is input in parallel and is converted into fixed-length code output data with word length. At the front stage of the code converter, a plurality of codes with word length of (i + l) or more are input in parallel and converted into fixed-length code output data with word length. A code conversion circuit for a variable length code, characterized in that a preprocessing circuit is provided to divide the code into several codes, and the code conversion unit is operated at a speed proportional to the number of divisions.