JP3032239B2 - Variable-length code decoding circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a variable-length code capable of decoding a variable-length code such as a Huffman code composed of a plurality of codes having different code lengths at a high speed. It relates to a decoding circuit.

[Conventional technology]

In order to efficiently transmit or record digital signals with a small number of bits, the code string representing data with a high probability of occurrence should be short, and the code string representing data with a low probability of occurrence should be long. A coding scheme set to be the minimum is known as a variable-length coding scheme or an unequal-length coding scheme. A typical example is the Huffman code.

FIG. 8 shows a configuration method of the Huffman code. As shown in FIG. 3A, first, a plurality of Huffman codes, for example, 6
Source information signals R _{1 to} R ₆ are arranged in descending order of occurrence probability, the two information source symbols having the smallest occurrence probability are collectively replaced by one information source symbol, and the combined probability is replaced with the new information source symbol. Probability of occurrence. In this example, replaced by a single information source symbols together and symbols R ₅ and R _6, are the combined probability and the probability of occurrence of new sources symbol. As a result,
A new set of source symbols with one less number of symbols is obtained.
Then, rearrange them again in descending order of occurrence probability,
Finally, the above-described processing is repeated until the symbol of the occurrence probability “1” remains. In this way, a "code tree" is created (Fig. (B)). Finally, codes "0" and "1" are assigned to each symbol according to branching (Fig. (C)), and encoding is completed. .

[Problems to be solved by the invention]

Decoding of the Huffman code generated in this manner is performed, for example, by inputting each bit of a code string of the Huffman code to be decoded one bit at a time and referring to a conversion table for each bit (see JP-A-64-60113). However, according to this method, the number of times of referring to the conversion table for a code string having a long code length increases, and there is a disadvantage that high-speed decoding cannot be performed. Therefore, it is not suitable for a system which needs to process a large amount of data at a high speed and display an image desired by a user on a screen instantly, such as a color image filing system.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a variable-length code decoding circuit that speeds up a decoding process by performing parallel processing of variable-length codes to be decoded in units of a plurality of bits.

[Means for solving the problem]

A variable-length code decoding circuit according to the present invention stores first and second data registers for sequentially inputting variable-length-coded input code strings in units of a plurality of parallel bits, and stores the input code strings in the first and second data registers. A barrel shifter that shifts each input code string to the LSB side by a designated number of bits and outputs the parallel multiple-bit code string, and detects a variable-length code from the output code string of the barrel shifter, and decodes the decoded data and code. Conversion means for outputting length data; and accumulation means for accumulating code length data output from the conversion circuit and supplying the accumulation result to the barrel shifter as shift bit number data. In order to perform cueing of a code string next to the variable-length code detected by the conversion means, each of the input codes corresponds to the number of bits specified by the shift bit number data. The first and second data registers shift the code string set in the first data register to the second data register when the accumulation result of the accumulation means exceeds a predetermined value. And the next new input code string is set in the first data register.

(Operation)

In the configuration of the present invention, the variable-length-encoded code string is fetched into the data register in units of a plurality of parallel bits, for example, 8 bits in parallel, and the first input code string is provided to the data input section of the barrel shifter. The columns are input to the barrel shifter's extended input. Therefore, two sets of code strings are input to the barrel shifter as parallel 16-bit code strings. The balal shifter extracts an 8-bit code string from the 16-bit code string and outputs it to the conversion means. The conversion means detects a variable-length code from the code string and outputs the corresponding decoded data and code length data. I do.
The code length data is input to the accumulating means, and is accumulated with the accumulated value of the code length data obtained so far.

Next, in order to find the beginning of the code string to be decoded next,
The accumulated value of the code length obtained by the accumulation means is supplied to the barrel shifter as shift bit number data. The barrel shifter shifts the input code string to the LSB side by the number of bits specified by the shift bit number data, extracts a new 8-bit code string, and outputs it to the conversion means. When the accumulated value of the code length data exceeds a predetermined value "8", the code string set in the first data register is set in the second data register, and the next new data is stored in the first data register. The input code string is set and the decoding process is repeated.

〔Example〕

FIG. 1 is a block diagram showing one embodiment of a variable length code decoding circuit according to the present invention. In this embodiment, a Huffman code will be described as an example of a variable length code.

The decoding circuit includes first and second data registers 1 and 2 which sequentially take in a Huffman-encoded input code sequence in units of a plurality of bits, and store the data in the first and second data registers 1 and 2. A barrel shifter 3 that shifts the code string by a predetermined number of bits according to shift bit number data to be described later and outputs the same, and a conversion circuit 4 that detects a Huffman code from the output of the barrel shifter 3 and outputs decoded data and code length data. And an accumulation circuit 5 for supplying shift bit number data to the barrel shifter 3 in order to find the beginning of a code string next to the code string currently being decoded, and the operation of these registers 1 to 5 And a control circuit 6 for controlling.

The data registers 1 and 2 are Huffman-coded parallel plural bits, for example, 8-bit input code strings ID _{0 to} ID.
_7, a register sequentially temporarily stores series two stages by the load signal LD ₁ from the control circuit 6.

Barrel shifter 3, the data input unit 3 stored code sequence in the data register 2 is inputted as the code string BD ₀ ~BD ₇
a, the code string stored in the data register 1 is a code string BD ₈ to
Extended input unit 3b which is input as a BD _15, the code string BD ₀ ~BD ₇ a predetermined control section 3c and the code sequence shift bit number of data SF ₀ ~BF ₃ for causing the number of shift bits are input HD ₀ ~ H
A data output unit 3d which D ₇ is output. Barrel shifter 3 code string BD ₀ ~BD ₇ was shifted to the number of bits BD ₀ side bit specified by the data SF ₀ ~BF _3, compensates for the code string BD ₈ ~BD ₁₅ vacated bit position code string HD outputted from the data output unit 3d as _{0 ~HD 7.} At this time, since the barrel shifter 3 can shift the input code string in a fixed time irrespective of the number of bits to shift, high-speed processing can be performed as compared with a shift register that shifts one bit by one clock pulse.

The conversion circuit 4 includes a binary tree circuit 41, as shown in FIG.
This is a PLA (Programmable Logic Arrey) configuration circuit including a decoded data generation circuit 42 and a code length data generation circuit 43. The binary tree circuit 41 in the circuit for outputting a signal S ₁ to S ₁₆ indicative of the sensed Huffman code from a code string HD ₀ ~HD _7, as shown in FIG. 3, reference numeral HD ₀ is "0" When output (signal
S ₁ ) Inverter IN that becomes “1”, AND circuit A ₁ that outputs “1” when code HD _{0 to} HD ₁ is “10”, and code HD _{0 to} HD ₁ becomes “1”
"AND circuit A ₂ becomes, code HD ₀ ~HD ₂ is" 1 "output when the" 1 "output when the (symbol S _2)" 100 1 "become the AND circuit A _3,
..., the output when the sign HD ₀ ~HD ₇ is all bits "1" (signal
S ₁₆ ) It is composed of an AND circuit A ₂₈ which becomes “1”. Thus, if for example the code sequence HD ₀ ~HD ₇ is "11010000",
Since the first five-bit code strings HD _{0 to} HD ₄ are “11010”, the output (symbol S ₈ ) of the AND circuit A ₁₅ is “1”, and the other outputs are “0” and the Huffman code “ 11010 "is detected. As described above, the binary tree circuit 41 receives the input code string HD
_{0 ~HD 7} finds symbol corresponding to the first bit HD ₀ to FIG. 4 follow a "code tree" shown in (a) to, as shown in FIG. 4 (b), only the symbol “1”
Is performed. Also, the decrypted data generation circuit 42
A circuit for generating a decoded data OD ₀ ~OD ₇ of 8 bits from S ₁ to S _16, as shown in FIG. 5 (a), 8 pieces of the OR circuit OR
Consists _{1 ~OR 8,} it is configured such that the input-output relation shown in the code table of FIG. 5 (b). Further, the circuit for outputting the code length data generating circuit 43 is 4-bit code length data SL ₀ to SL ₃ showing the code length of the Huffman code decoded by the binary tree circuit 41, as shown in FIG. 6 (a) And four OR circuits OR
_{11 to} OR ₁₄ , and are configured to have the input / output relationship shown in the code table of FIG. 6 (b).

Accumulation circuit 5 in order to perform the beginning of the next code string of the code string that is currently decoding, the code string BD ₀ ~BD ₇ many bits BD
A circuit for outputting 4-bit shift bit number data SF _{0 to} SF ₃ indicating whether the shift is to be performed to the ₀ side, and includes an adder circuit 51 and an accumulation register 52. Adder circuit 51 is a circuit for adding the code length accumulated value stored in the code length data SL ₀ to SL ₃ and register 52 supplied from the conversion circuit 4, the addition result code length accumulated value in the register 52 If the addition result exceeds “8”, overflow data OVF is output. Stored code length accumulated value in the register 52 is supplied as a shift bit number of data SF ₀ - SF ₃ to the control terminal 3c of the barrel shifter 3.

The control circuit 6 is a circuit for controlling the operation of the register 1 to the accumulation circuit 5 sequentially takes an input code string ID ₀ ~ID ₇ outputs a load signal LD ₁ to the register 1 and 2 to the data register 1 and 2, The load signal LD ₂ is output to the accumulation register 52 of the accumulation circuit 5, and the addition result of the addition circuit 51 is stored in the accumulation register 52. When the addition result of the addition circuit 51 exceeds “8”, the overflow data OVF is supplied from the addition circuit 51.

Next, the operation of the embodiment having this configuration will be described with reference to a specific example of an input code string.

Now, an input code string ID ₀ ~ID ₇ which are Huffman coding,
As shown in FIG. 7 (a), if the first column is “01100111”, the second column is “11010000”, the third column is “01111010”, the fourth column is “10111110”,. , the control circuit 6 first column of the code string by the first load pulse of the load signal LD ₁ supplied is set in the data register 1 from the subsequent second first column of the code string data register by the load pulse 2, the second code string is set in the data register 1. Therefore, the first code string “01100111” and the second code string “11010” are stored in the barrel shifter 3.
000 "of 16-bit code sequence BD ₀ ~BD ₁₅ (" 011001111101000
0 ") is input (FIG. (B)). The number of shift bits data SF ₀ input to the control unit 3c of the barrel shifter 3 - SF
_3, because the first is "0" (decimal), the code string BD ₀ ～BD
₇ is output to the conversion circuit 4 as an output code string HD ₀ ~HD ₇ (FIG. (C)).

The conversion circuit 4 detects that in a binary tree circuit 41 first bit HD ₀ code sequence HD ₀ ~HD ₇ is Huffman code "0",
And outputs the corresponding symbol S _1. Decoded data generating circuit 42 and the code length data generating circuit 43 outputs the code value "1" and the decoding length "1" receives the signal S _1.

The accumulating circuit 5 adds the code length “1” to the accumulated code length value stored in the register 52 by the adding circuit 51, and stores the addition result in the register 52. Then, the cumulative value stored in the register 52, and inputs the shift bit number of data SF ₀ - SF ₃ to the control unit 3c of the barrel shifter 3. In the present example, since the accumulated code length value stored in the register 52 is “0”, the addition result is “1”, and the shift bit number data “1” is supplied to the barrel shifter 3.

The barrel shifter 3 outputs the shift bit number data “1”.
Shifts the code sequence BD ₀ ~BD ₁₅ to 1-bit left (LSB side) receives the code string BD ₁ ~BD ₈ a new code sequence HD ₀ ~HD ₇ ( "11
001111 ") (FIG. 6D).
Detects that the code sequence HD ₀ ~HD ₅ out of the code string HD ₀ ~HD ₇ is Huffman code "110011", the decoded data generating circuit 42
And supplies the symbol S ₇ to the code length data generating circuit 43. Decoded data generating circuit 42 and the code length data generating circuit 43 outputs the symbol S ₇ receiving and decoding value "16" and the code length of "6", and supplies the accumulation circuit 5.

The accumulation circuit 5 adds the code length "6" to the code length accumulated value "1" stored in the register 52 by the addition circuit 51, and stores the addition result "7" in the register 52. Then, to the control section 3c of the barrel shifter 3 accumulated value this stores "7" as the shift bit number of data SF ₀ - SF _3.

The barrel shifter 3 outputs the shift bit number data “7”.
The code BD ₀ ~BD ₁₅ now shifts to 7 bits left by code string BD ₇ ~BD ₁₄ a new code sequence HD ₀ ~HD ₇ ( "11101
000 ") is output (FIG. (E)). The binary tree circuit 41 code string HD ₀ ~HD ₃ Huffman codes of the code string HD ₀ ~HD _7" 11
10 and supplies the decoded data generating circuit 42 and the code length data generating circuit 43 as a "" symbol S ₁₁ detects that the ". Decoded data generating circuit 42 is decoded values In response to the symbol S _11" 60 , And the code length data generation circuit 43 similarly outputs a code length “4”.

The accumulating circuit 5 has a code length “4” and a register 52
And outputs the overflow data OVF indicating that the added value exceeds “8” to the control circuit 6 and the addition result “3”.
Is stored in the register 52. The control circuit 6 supplies a load signal LD ₁ to the data register 1 and 2 receives the overflow data OVF, sets the code string of the second row, which is set in the data register 1 to the data register 2, data register The code string of the third column is set to 1. Accordingly, the barrel shifter 3 is inputted is "1101000001111010" as a code string BD ₀ ~BD ₁₅ (Fig. (F)). The barrel shifter 3 shifts the code strings BD _{0 to} BD ₁₅ toward the LSB side by the shift bit number data “3” supplied from the register 52 by 3 bits, and converts the code strings BD _{3 to} BD ₁₀ to a new code string H.
It is output as D _{0 to} HD ₇ (“10000011”) (FIG. 9G).

Hereinafter, the same operation is repeated, and eventually the code strings of the first to fourth columns shown in FIG. 7A are converted into the respective symbols shown in FIG. Get the data.

〔The invention's effect〕

According to the present invention, the encoded variable-length code is processed in units of a plurality of parallel bits, so that one code length can be processed in one process, and the decoding process can be speeded up. In addition, since the next code string is searched for by the barrel shifter, the next code string can be searched for in a fixed time regardless of the code length, and the decoding process can be further speeded up. Can be done.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a variable-length code decoding circuit according to the present invention, FIG. 2 is a block diagram of a conversion circuit shown in FIG. 1, and FIGS. 3 and 4 are shown in FIG. FIG. 5 illustrates the configuration and operation of the binary tree circuit, FIG. 5 illustrates the configuration and operation of the decoded data generation circuit illustrated in FIG. 2, and FIG. 6 illustrates the code length data generation circuit illustrated in FIG. FIG. 7 is a diagram illustrating the configuration and operation, FIG. 7 is a diagram illustrating the operation of this embodiment, and FIG. 8 is a diagram illustrating the configuration method of the Huffman code. 1,2 ... data register, 3 ... barrel shifter, 4 ...
Conversion circuit, 5: accumulation circuit, 6: control circuit.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H03M 7/40

Claims (1)

(57) [Claims] A first and a second data register for sequentially taking in an input code string that has been subjected to variable length coding in units of a plurality of parallel bits, and an input code string stored in the first and second data registers, A barrel shifter that shifts to the LSB side by the designated number of bits and outputs the parallel multiple-bit code string, and a conversion that detects a variable-length code from the output code string of the barrel shifter and outputs decoded data and code length data thereof Means, and accumulating means for accumulating the code length data output from the conversion circuit, and supplying the accumulation result to the barrel shifter as shift bit number data, wherein the barrel shifter is a variable detector detected by the conversion means. In order to perform cueing of the code sequence next to the long code, each of the input code sequences is LS
The first and second data registers shift to the B side, and when the accumulation result of the accumulation means exceeds a predetermined value, the code string set in the first data register is shifted to the second data register. A variable length code decoding circuit, wherein the variable length code is set in a register and the next new input code string is set in the first data register.