JPH0423521A - Decoding circuit for variable length code - Google Patents

Abstract

PURPOSE:To rapidly execute decoding processing by processing coded variable length codes in each parallel plural bits so that one code length can be processed by one processing. CONSTITUTION:Variable length coded code strings are entered into data registers l, 2 in each parallel 8 bits e.g. the 1st input code string is inputted to the data input part 3a of a barrel shifter 3 and the 2nd input code string is inputted to the expanded input part 3b of the shifter 3. Namely, two code strings are inputted to the shifter 3 as a parallel 16-bit code string. The shifter 3 extracts an 8-bit code string from the 16-bit code string and outputs the extracted code string to a conversion circuit 4, which detects a variable length code from the inputted code string and outputs its corresponding decoding data and code length data. Since variable length codes to be decoded are processed in each plural bits in parallel, the decoding processing can rapidly be executed.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention is a variable-length code that can decode a variable-length code such as a Huffman code, which is made up of a group of codes with a plurality of different code lengths, at high speed. Regarding decoding circuits.

[Conventional technology]

In order to efficiently transmit or record digital signals with a small number of bits, code strings representing data with a high probability of occurrence are set short and code strings representing data with a low probability of occurrence are set long, so that the average code length as a whole is A coding system that sets the minimum length is known as a variable length coding system or an unequal length coding system. A typical example is the Huffman code.

FIG. 8 shows a method of constructing a Huffman code. In the Huffman code, as shown in Figure (a), a plurality of M information source signals R1 to R6, for example, 6, are first arranged in descending order of probability of occurrence, and the two information source symbols with the lowest probability of occurrence are selected. All information source symbols are replaced with one information source symbol, and the combined probability is taken as the occurrence probability of the new information source symbol. In this example, symbols R5 and R6 are collectively replaced with one information source symbol, and their combined probability is used as the occurrence probability of the new information source symbol. As a result, a new set of information source symbols with one fewer symbol is obtained. Next, the items are sorted again in descending order of probability of occurrence, and the above-described process is repeated until the symbol with probability of occurrence "1" remains at the end. In this way, a "code tree" is created (Figure (b)).Finally, codes of "0゛ and Pa1" are assigned to each symbol according to the branching (Figure (C)), and the encoding is completed.

[Problem to be solved by the invention]

The Huffman code generated in this manner is decoded, for example, by inputting each bit of the code string of the Huffman code to be decoded one by one and referring to a conversion table for each bit (see Japanese Patent Laid-Open No. 64-60113). However, this method has the disadvantage that for code strings with long code lengths, the number of times the conversion table is referred to increases, making it impossible to perform high-speed decoding processing. Therefore, it is not suitable for a system such as a color image filing system that processes a large amount of data at high speed and that requires the user to instantly display the desired image on the screen.

An object of the present invention is to provide a variable-length code decoding circuit that speeds up the decoding process by processing the variable-length code to be decoded in parallel in units of multiple bits.

[Means to solve the problem]

A variable-length code decoding circuit according to the present invention includes first and second data registers that sequentially take in a variable-length encoded input code string in units of multiple bits in parallel, and stores the variable-length code in the first and second data registers. A barrel shifter that shifts each input code string to the LSB side by a specified number of bits and outputs it as the parallel multi-bit code string; detects a variable length code from the output code string of the barrel shifter, and detects the decoded data and the code; converting means for outputting length data; and accumulating means for accumulating the code length data output from the converting circuit and supplying the accumulated result to the barrel shifter as shift bit number data; In order to locate the beginning of the next code string of the variable length code detected by the converting means, each input code string is shifted to the LSB side by the number of bits specified by the shift bit number data. and a second data register sets the code string set in the first data register to a second data register when the accumulated result of the accumulator exceeds a predetermined value; The next new input code string is set in data register 1.

[For production]

In the configuration of the present invention, a variable-length encoded code string is taken into the data register in units of parallel plural bits, for example, parallel 8 bits, and the first input code string is input to the data input section of the barrel shifter, and the second input code string is input to the data input section of the barrel shifter. The columns are each input to an expansion input of the barrel shifter. Therefore, two sets of code strings are input to the barrel shifter as parallel 16-bit 1- code strings. The parallel shifter extracts an 8-bit code string from this 16-bit code string and outputs it to the conversion means, and the conversion means detects a variable length code from this code string and outputs the corresponding decoded data and code length data. do. The code length data is input to the accumulator and is accumulated with the accumulated value of the code length data obtained so far.

Next, in order to locate the beginning of the code string to be decoded next, the cumulative value of the code length obtained by the accumulating means is supplied to the barrel shifter as shift bit number data.

The barrel shifter shifts the input code string to the LSB side by the number of bits specified by this shift bit number data, and creates a new 8 bits.
The bit code string is extracted and output to the conversion means. When the accumulated value of the code length data exceeds the predetermined value "8", the code string set in the first data register is set in the second data register, and the next new data is stored in the first data register. Set the input code string and repeat the decoding process.

〔Example〕

FIG. 1 is a block diagram showing an embodiment of a variable length code decoding circuit according to the present invention. Note that this embodiment will be explained using a Huffman code as an example of a variable length code.

This decoding circuit includes first and second data registers 1 and 2 that sequentially take in a Huffman-encoded input code string in units of multiple bits in parallel, and data stored in the first and second data registers 1 and 2. A barrel shifter 3 that shifts a code string by a predetermined number of bits based on shift bit number data to be described later and outputs the result, and a conversion circuit 4 that detects a Huffman code from the output of the hull shifter 3 and outputs its decoded data and code length data. Then, in order to cue the code string next to the code string currently being decoded, an accumulator circuit 5 supplies shift bit number data to the barrel shifter 3, and the operations of these registers 1 to 5 are controlled. It is composed of a control circuit 6 for controlling.

Data registers 1 and 2 are Huffman encoded parallel multiple bits, for example, an 8-bit input code string IDo=ID
This is a two-stage register in series that sequentially and temporally stores 7 in response to a load signal LDt from the control circuit 6.

The barrel shifter 3 has a data input section 3a to which the code string stored in the data register 2 is input as a code string BDo''-BD7, and a data input section 3a to which the code string stored in the data register 1 is input as a code string BDe to BD. It includes an extended input section 3b, a control section 3C to which shift bit number data SFO to SF3 for shifting the code strings BDo to BD7 by a predetermined number of bits is input, and a data output section 3d to which the code string HDo=HD7 is output. .Barrel shifter 3 is code string BD
o'' BD7 is shifted to the bit BDO side by the number of bits specified by data SFo to SFa, and the vacant bit positions are supplemented with code strings BDa to BD, . . . to create code strings HDo to HD7.
The data output unit 3d outputs the data as the data output unit 3d. At this time, since the barrel shifter 3 can shift the manual code string in a fixed time regardless of the number of bits to be shifted, high-speed processing is possible compared to a shift register that shifts one bit with one clock pulse.

As shown in FIG. 2, the conversion circuit 4 includes a binary tree circuit 41,
Decoded data generation circuit 42 and code length data generation circuit 4
PLA (Programmable) consisting of 3
This is a circuit with a LogicArray) configuration. The binary tree circuit 41 is a circuit that detects a Huffman code from the code string HDo"-HD7 and outputs the corresponding symbols Sl to SI6. As shown in FIG. S1) Inverter IN, code HD which becomes “'1゛”
AND circuit A1 outputs "1" when o=HDt is "10", and outputs "1" when code HDo~HD1 is "11'"
AND circuit A2 which becomes 1゛, code HDO-HD2 becomes '1
AND circuit A3 whose output (symbol S2) is 1'' when the signal is ``00°'', . It consists of

Therefore, for example, the code string HDo to HD7 is "'11010
000”, the first 5-bit code string HDo=H
Since D+ is '1101-0', AND circuit A1
The output of 5 (symbol Ss) is 1゛, and the other outputs are “
0", and the Huffman code "'11010" is detected. In this way, the binary tree circuit 41 receives the input code string HD.
Find the corresponding symbol by following the "code tree" shown in FIG. 4(a) from HDo (starting with the first pip for HD7), and as shown in FIG. 4(b), change only that symbol to " The decoded data generation circuit 42 is a circuit that generates decoded data ODO to OD7 of 8 pins I from the symbols S1 to S16, as shown in FIG. 5(a). Consisting of eight OR circuits OR1 to OR8, the fifth
It is configured to have the input/output relationship shown in the code table in Figure (b). Further, the code length data generation circuit 43 is a circuit that outputs 4-bit code length data 5Lo=SLa indicating the code length of the Huffman code decoded by the bifurcation circuit 41, as shown in FIG. 6(a). 4 OR circuits OR,, ~O
R14, and is configured to have the input/output relationship shown in the code table of FIG. 6(b).

The accumulator circuit 5 uses a 4-bit shift bit number indicating how many bits of the code strings BDo to BD7 should be shifted to the BDo side in order to cue the next code string of the code string currently being decoded. This circuit outputs data SFo to SFs and is composed of an adder circuit 51 and an accumulation register 52. The addition circuit 51 receives the code length data SL supplied from the conversion circuit 4.
A circuit that adds o~SL3 and the code length accumulated value stored in the register 52. The addition result is stored in the register 52 as the code length accumulated value, and if the addition result exceeds "8", overflow data is stored. Output OVF. register 5
The code length accumulated value stored in 2 is supplied to the control terminal 3C of the barrel shifter 3 as shift bi/so If data 5Fo-3F3.

Control circuit 6 is a circuit that controls the operations of register 1 to accumulation circuit 5, and sends a load signal LD to registers 1 and 2.
1 and sequentially captures the input code strings ID0-ID7 into data registers 1 and 2, and also outputs a load signal LD2 to the accumulation register 52 of the accumulation circuit 5 to load the input code strings ID0-ID7 into the data registers 1 and 2.
The result of addition of 1 is stored in the accumulation register 52. Further, when the addition result of the addition circuit 51 exceeds "8", overflow data OVF is supplied from the addition circuit 51.

Next, the operation of the embodiment having this configuration will be explained using a specific example of an input code string.

Now, the input code string TD is Huffman encoded.

~ID7, as shown in Figure 7(a), the first column is "
01100111", the second column is "'11010000
°゛, 3rd column is '01111010', 4th column is 1
0111110''',..., the first load pulse of the load signal LD1 supplied from the control circuit 6 sets the code string in the first column in the data register 1, and the code string in the first column is set in the data register 1 by the second load pulse. The code string in the first column is set to data register 2, and the code string in the second column is set to data register 1. Therefore, the barrel shifter 3 stores the code string "01100111" in the first column and the code string in the second column. The code string “11010000” is a 16-bit code string BDo ~ BD+s (“0110011111
010000") (Figure (b)). Since the shift bit number data SFo to SFa input to the control unit 3C of the barrel shifter 3 is initially "0" (decimal), the code string BDo to BD7 is the output code string HDo-H
It is output as is to the conversion circuit 4 as D7 (Figure (C)
).

In the conversion circuit 4, the binary tree circuit 41 converts the code string HD.

~Detects that the first bit HDo of HD7 is a Huffman code "0" and outputs the corresponding symbol S1.Decoded data generation circuit 42 and code length data generation circuit 43 receive this symbol S1 and generate a decoded value "1". ” and code length “1j”.

The accumulating circuit 5 adds the code length "1" to the code length accumulated value stored in the register 52 using an adder circuit 51, and stores the addition result in the register 52. And register 524
The stored accumulated value is shifted bit number data 5FO-
It is input to the control section 3C of the barrel shifter 3 as 3F3.

In the present example, the code length accumulated value stored in the register 52 is "0", so the addition result is "1", and shift bit number data "1" is supplied to the barrel shifter 3.

The barrel shifter 3 receives this shift bit number data "1" and shifts the code string BDo-BD, , 1 bit to the left (L
SB side), and the code strings BDt to BD8 are converted to a new code string HDo "HD? ("11001111°")
) (Figure (d)). The binary tree circuit 41 detects that the code strings HDO to HDs among the code strings HD and -HD7 are Huffman codes "'110011", and supplies the symbol S7 to the decoded data generation circuit 42 and the code length data generation circuit 43. do. The decoded data generation circuit 42 and the code length data generation circuit 43 receive this symbol S7 and generate the decoded value "
16'' and code length ``6'' are output and supplied to the accumulator circuit 5.

The accumulating circuit 5 adds the code length "6" to the code length accumulated value "1" stored in the register 52 using the adding circuit 51, and stores the addition result "7" in the register 52. Then, this stored accumulated value "7" is shifted to the hit number data 5Fo.
-3Fa is supplied to the barrel shifter 30 control unit 3C.

The barrel shifter 3 shifts the code string BDo-BIIl+s to the left by 7 bits using this shift hit number data "7" and outputs the code string BD7 to BD,4 as a new code string HDo"-HD7 ("11101000"). (Figure (e)).The binary tree circuit 41 generates the code string HDo
It is detected that the code string 1DO to 11D3 of "HD7" is a Huffman code "1110" and the symbol S I+ is set as "'1" and is supplied to the decoded data generation circuit 42 and code length data generation circuit 43.Decoding Data generation circuit 4
2 receives this symbol S I+ and outputs the decoded value "60", and similarly the code length data generation circuit 43 outputs the code length "4".

The accumulator circuit 5 inputs the code length "4" and the register 5 in the adder circuit 51.
The code length accumulated value "7" stored in 2 is added, and overflow data OVF, which means that the added value exceeds "8", is output to the control plate circuit 6, and the addition result is "3". is stored in the register 52. The control plate circuit 6 receives this overflow data OVF and registers the data register 1.
and load signal 1 to 2. Dl is supplied, the second column code string set in data register 1 is set in data register 2, and the third column code string is set in data register 1. Therefore, the barrel shifter 3 has the code string B.
Do~BDI, as”11010000011110
10" is input (FIG. (f)). The barrel shifter 3 stores this code string B D o = B D +s in the register 52.
L by the shift bit number data “3” supplied from
3-bit shift 1-S on B side, code string BDa to BD
1o as a new code string HDo ~ HD7 ("1000
0011″”) (Figure (g)).

Thereafter, similar operations are repeated, and eventually the code strings of the first to fourth columns shown in FIG.
h) to obtain corresponding decoded data.

〔Effect of the invention〕

According to this invention, the encoded variable length code is processed in units of parallel multiple bits, so one code length can be processed in one process, and the decoding process can be speeded up. . In addition, since the barrel shifter is used to locate the beginning of the next code string, it is possible to locate the beginning of the next code string in a fixed amount of time regardless of the code length, further speeding up the decoding process. I can do it.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a variable length code decoding circuit according to the present invention, FIG. 2 is a block diagram of the conversion circuit shown in FIG. 1, and FIGS. 3 and 4 are shown in FIG. Figure 5 is a diagram explaining the configuration and operation of the binary tree circuit; Figure 5 is a diagram explaining the configuration and operation of the decoded data generation circuit shown in Figure 2; Figure 6 is a diagram explaining the configuration and operation of the code length data generation circuit shown in Figure 2. FIG. 7 is a diagram illustrating the operation of this embodiment. FIG. 8 is a diagram illustrating a Huffman code construction method. 2...Data register, 3...Barrel shifter, 4...Conversion circuit, 5...Accumulation circuit, 6...Nil control circuit.

Claims (1)

[Scope of Claims] First and second data registers that sequentially take in variable-length coded input code strings in units of parallel plural bits, and each input code string stored in the first and second data registers. , a barrel shifter that shifts to the LSB side by a specified number of bits and outputs it as the above-mentioned parallel multi-bit code string, and detects a variable length code from the output code string of the barrel shifter and outputs its decoded data and code length data. converting means; and an accumulating means for accumulating the code length data output from the converting circuit and supplying the accumulated result to the barrel shifter as shift bit number data, the barrel shifter detecting the data by the converting means. In order to locate the beginning of the next code string of the variable length code, shift each input code string to the LSB side by the number of bits specified by the shift bit number data,
The first and second data registers set the code string set in the first data register in the second data register when the accumulation result of the accumulation means exceeds a predetermined value, and A variable length code decoding circuit characterized in that a next new input code string is set in a first data register.