JP2594699B2 - 5B6B code rule inversion circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a 5B6B code rule inverse conversion circuit which is mainly used for digital transmission and reversely converts a 6-bit signal subjected to 5B6B code rule conversion into an original 5-bit signal. At the time of the inverse rule conversion, instead of detecting all 6-bit patterns, the pattern is divided into upper 3 bits and lower 3 bits, and a 6-bit mark rate is detected from those patterns to reduce the number of detected patterns. In order to simplify the circuit, a signal consisting of a series of bits converted by the 5B6B
First and second decoders that generate eight patterns of signals from three bits out of the six bits that are divided into bits, respectively, and the six divided signals from eight patterns of signals from the first and second decoders, respectively. A mark ratio detection circuit for detecting a bit mark ratio, and a code inverse conversion for performing an inverse conversion of the 5B6B coding rule in accordance with the mark ratio detected by the mark ratio detection circuit and converting the divided 6 bits into a 5-bit signal. Circuit, a 5-bit signal inversely transformed by the code inverse transformation circuit according to the mark rate detected by the mark rate detection circuit, a high-order 5 bit signal of the divided 6 bits, or an error signal. And a select circuit for selecting and outputting one of the following.

[Industrial application field] The present invention is mainly used for digital transmission, and is used for 5B6B
The present invention relates to a 5B6B coding rule reverse conversion circuit that reversely converts a 6-bit signal subjected to a coding rule conversion into an original 5-bit signal.

[Related Art] Generally, in a regenerative repeater used in digital transmission,
A self-timing scheme for extracting a timing wave from a received pulse train itself is widely used. In such a timing extraction method, when the input code sequence is a continuous zero code such as “000...”, Timing information may be lost on the transmission path.

Therefore, in digital transmission, in order to avoid such loss of timing information, 5B6B
The coding rule conversion is performed to suppress the continuation of the zero sign. Here, the 5B6B coding rule conversion means that a digital signal sequence is divided into 5 bits, and the 5-bit signal is converted into 6-bit signals according to a 5B6B coding rule conversion pattern as shown in FIG.
This is to convert it into a 5B6B code signal.

At the time of reception, the received digital signal sequence is divided into 6-bit units, and the inverse conversion of the 5B6B coding rule is performed.
I try to get a bit signal.

 FIG. 14 shows a conventional 5B6B coding rule inversion circuit.

As shown in the figure, in the conventional 5B6B coding rule inversion circuit,
First, the mark rate of the 6-bit signal to be inversely converted is detected, and then the 5B6B coding rule inverse conversion is performed accordingly. Here, the mark ratio is the ratio of “on” bits in 6 bits, and in the figure, 1/6, 2/6
Is displayed as a fraction.

That is, the conventional 5B6B coding rule inverse conversion circuit has a mark rate that is not in the conversion pattern of FIG. 13, that is, a mark rate of 0/6, 1/6,
2 / 6,4 / 6,5 / 6 or 6/6 (However, the mark ratio 2 / 6,4 / 6 none of the conversion pattern of Fig. 13) the signal S ₈₈ when the detected were detected The output first detection circuit 11a and the mark rate in the conversion pattern of FIG. 13, that is, the mark rate 2/6, 3 /
Detecting a 6 or 4/6, and outputs the signal S ₈₆ when the mark rate is 2/6 or 4/6, the signal S ₈₇ when the mark rate is 3/6
5B6B and the second detection circuit 11b for outputting a 6-bit signal S ₈₁ of D1~D6 when the signal S ₈₆ is issued from the second detection circuit 11b
Code inverse conversion circuit 12 and the signal S ₈₅ when normally the signal S ₈₇ from the second detection circuit 11b outputs a signal S ₈₂ as the signal S ₈₃ has been issued to output coding rule inverse conversion as 5-bit signal S ₈₂ ( D
A select circuit 13 which selectively outputs the 5-bit signal) to 1~D5 as the signal S _83, signal when normally the first detection circuit 11a signal S ₈₈ from the output signal S ₈₃ as the signal S ₈₄ is issued Select circuit 1 that selects and outputs "10101" as signal _S84
Consists of four.

As described above, in the conventional 5B6B coding rule inversion circuit, the mark rate of the 6-bit 5B6B code signal is detected, and if the mark rate is 2/6, 3/6 or 4/6, FIG. Perform 5B6B coding rule reverse conversion based on the conversion pattern, and mark ratio is 0 / 6,1 /
If it is 6,2 / 6,4 / 6,5 / 6 or 6/6 (however, the mark ratio 2 / 6,4 / 6 is not in the conversion pattern of Fig. 13), then "1010
It is converted to a 5-bit signal of "1".

[Problem to be Solved by the Invention] However, in such a conventional 5B6B coding rule inversion circuit, when the first detection circuit 11a and the second detection circuit 11b detect each mark rate, a 6-bit signal is used. Since detection is performed for all patterns (64 patterns), there is a problem that the circuit scale becomes large and the circuit includes many redundant circuits.

The present invention has been made in view of such circumstances, and does not detect all 6-bit patterns at the time of 5B6B coding rule inversion, but separates them into upper 3 bits and lower 3 bits, An object of the present invention is to provide a 5B6B coding rule inverse conversion circuit in which a 6-bit mark ratio is detected from a pattern and the number of detection patterns is reduced to simplify the circuit.

[Means for Solving the Problems] The invention according to claim 1 of the present application divides a signal consisting of a series of bits converted into a 5B6B code rule into 6 bits, and starts from the upper 3 bits of the 6 bits. A first decoder 1a for generating eight patterns of signals, a second decoder 1b for generating eight patterns of signals from the lower three bits of the divided six bits, and first and second decoders 1a and 1b, respectively. A mark rate detecting circuit 2 for detecting the divided 6-bit mark rate from the signal of 8 patterns, and performing the inverse conversion of the 5B6B coding rule in accordance with the mark rate detected by the mark rate detecting circuit 2 to perform the divided 6 bit Code conversion circuit 3 for converting the signal into a 5-bit signal, and mark ratio detection circuit 2
In accordance with the mark rate detected by the above, one of a 5-bit signal inversely transformed by the code inverse transformation circuit 3, an upper 5 bits signal out of the divided 6 bits, or an error signal is selected. This is a 5B6B coding rule reverse conversion circuit including a select circuit 4 that outputs the data.

The invention according to claim 2 of the present application is a first mark ratio for dividing a signal consisting of a series of bits subjected to 5B6B coding rule conversion into 6 bits and detecting a mark ratio of upper 3 bits for the divided 6 bits. The detection circuit 51 and the divided 6
Second to detect mark ratio of lower 3 bits for bit
The mark rate detection circuit 52, the first mark rate detection circuit 51 and the second
This is a 5B6B coding rule inversion circuit including a 6-bit mark rate determination circuit 53 for determining the divided 6-bit mark rate according to the mark rate detected by the mark rate detection circuit 52.

[Operation] According to the invention of claim 1 of the present application, the signal subjected to the 5B6B code rule conversion is divided into 6 bits, and the first and second decoders 1a and 1b output the upper 3 bits of the 6 bits. , A signal of eight patterns is generated from the signal of the lower three bits, respectively, and a signal of eight patterns is generated. The mark rate detection circuit 2 detects a divided six-bit mark rate from the signal of each of the eight patterns. .

Then, according to the mark rate, the select circuit 4 selects one of the five-bit signal inversely converted by the code inverse conversion circuit 3, the upper five bits of the divided six bits, or the error signal. One is selected and output.

Therefore, a 6-bit signal is divided into upper 3 bits and lower 3 bits, and a 6-bit mark rate is detected from these patterns, so that the number of detected patterns can be reduced, thereby reducing the circuit scale. It can be reduced than before.

According to the invention of claim 2 of the present application, the signal subjected to the 5B6B code rule conversion is divided into 6 bits each, and the first mark ratio detection circuit 51 determines the mark ratio of the upper 3 bits for the divided 6 bits. And the second mark ratio detection circuit 52 detects the mark ratio of the lower 3 bits for each of the divided 6 bits.

Then, the 6-bit mark rate determination circuit 53 determines the divided 6-bit mark rate according to the mark rates detected by the first mark rate detection circuit 51 and the second mark rate detection circuit 52.

Therefore, the 6-bit signal is divided into upper 3 bits and lower 3 bits, and the 6-bit mark rate is determined from the mark rates. Therefore, the number of detection patterns can be reduced, thereby increasing the circuit scale. Can be reduced more than before.

Hereinafter, the present invention will be described in detail with reference to embodiments shown in the drawings. Note that the present invention is not limited to this.

FIG. 1 is an explanatory diagram showing the basic structure of a 5B6B coding rule inverse transform circuit as one embodiment of the present invention.

In FIG. 1, 1a and 1b are the first and second 3LINE to
8LINE Decoder / Demultiplexer (hereinafter abbreviated as 3: 8 decoder), 2 is a mark rate detection circuit, 3 is a code reverse conversion circuit, and 4 is a select circuit.

The first 3: 8 decoder 1a is 6-bit signal S ₁ (D1~D
From the upper 3 bits of the 6) (D1 to D3), to generate a converted signal S ₅ of 8 pattern, the second 3: 8 decoder 1b, the signal S
From the lower 3 bits of the ₁ (D4 to D6), to generate a converted signal S ₆ of 8 pattern.

The mark ratio detection circuit 2 converts the conversion signal of 8 patterns × 2
From S ₅ and S ₆ , when the mark rate in the 5B6B coding rule conversion pattern shown in FIG. 13, that is, the mark rate 2/6 or 4/6 is detected, the signal S ₇ is output, and the conversion pattern shown in FIG. Mark ratios that do not exist, that is, mark ratios 0/6, 1/6, 2/6, 4/6, 5/6 or 6/6 (however, for mark ratios 2/6, 4/6 outputs a signal S ₈ when it detects having no pattern).

The sign inversion circuit 3 outputs the signal S ₇ from the mark rate detection circuit 2.
Within when issued, the signal S ₁ 5B6B coding rule inverse conversion based on the conversion pattern of Fig. 13, and outputs a signal S ₂ of 5 bits.

When the signal S ₇ is output from the mark ratio detection circuit 2, the select circuit 4 selects and outputs the signal S ₂ as it is as the signal S ₃ , and when the signal S ₈ is output from the mark ratio detection circuit 2, the signal “ select output 10101 to "as the signal S _3, 5 bits from the mark rate detecting circuit 2 when no issued both signals S ₇ and the signal S ₈ is regarded as the mark rate 3/6, until the signal S ₄ (D1 to D5 selectively outputs the signal) as the signal S _3.

Thus, in this embodiment, divided 5B6B code signals S ₁ of six bits to 3 bits, the first, second 3: 8 decoders 1a, converted signal 16 pattern 1b (8 pattern × 2)
S ₅ and S ₆ are generated. Then, the mark rate detection circuit 2 detects all patterns (44 patterns) other than the mark rate 3/6, and outputs a signal S ₈ (error signal) when the conversion pattern shown in FIG. divided into a signal S ₇ when it is in the conversion pattern of Fig., the signal S by detecting the signal S _7
2, the signal "10101" by detecting the signal S _8, the signal S ₄ to be detected both signals S ₇ and the signal S _8, selected by the select circuit 4, respectively, outputs a 5-bit signal S ₃ I am trying to do it.

Thereby, in the mark ratio detection circuit 2, the mark ratio
There is no need to detect 3/6. In addition, by using the first and second 3: 8 decoders 1a and 1b, the mark ratio can be detected by a simple combination of numerals as shown in FIG.

In the mark ratio detection circuit 2, a 3-bit unit (D1 to D1) is used.
In order to detect the mark rate by using D3 and D4 to D6 (three-bit signals), the mark rate is calculated in each bit pattern shown in FIG. A pattern occurs. This means that the signals D1 to D3 are “000”
In the case of, the signals of D4 to D6 are (A) patterns (“001”, “010”,
"100"), the mark rate becomes 1/6, and the signals D1 to D3 are (H) patterns ("001", "010").
In any of the cases, if the signals D4 to D6 are any of the patterns in the (A) pattern, the mark ratio is 2/6.

As described above, the mark ratio detection circuit 2 is configured as shown in FIG.
As shown in (a), when the pattern (A) is detected, D1 to
If the signal of D3 is "000", the mark rate is 1/6, and if it is the (H) pattern, the mark rate is 2/6, so that the circuit configuration can be simplified.

In the sign inversion circuit 3, the mark ratio is 2/6, 4/6 (first
When detecting the pattern in the conversion pattern shown in FIG. 3, the output signal S ₂ from the sign inverse conversion circuit 3 is used as it is as the output signal S ₃
Becomes Since the mark ratio 2/4 and 4/6 is the same signal when inverted, the code inverse conversion circuit 3 at the time of detection of the mark rate 2/6 type raw signals S _1, except mark ratio 2/6 performs conversion by inputting by inverting the signals S _1, if any. In the case of the inverse conversion, the inverse conversion is performed by detecting a pattern having a mark rate of 2/6. However, since the mark rate 2/6 has only two “1” s, “1” is set. The circuit is configured to perform inverse conversion depending on the position.

The select circuit 4 uses five 3: 1 select circuits instead of using ten conventional 2: 1 select circuits. The select circuit 4 is required for 5 bits all the output signals S _3, conventionally, the circuit scale to have employed two-step selection circuit was larger, 3: 1 by using a select circuit, The circuit configuration is such that the circuit scale and the number of redundant circuits can be reduced.

FIG. 3 to FIG. 7 are electric circuit diagrams of the 5B6B coding rule inverse transform according to an embodiment of the present invention.

Figure 3 is the first and second 3: 8 decoders 1a, 1b is a circuit diagram, shown in Figure, the 5B6B code signals S ₁₁ to S ₁₆ of six bits (D1 to D6), first and Using the second 3: 8 decoder 1a, 1b
16 signal pattern (eight patterns × 2) S ₅₀ ~S ₅₇ and S ₆₀
To convert to ~S _67. The converted signal S ₅₀ to S ₅₇ and S
From ₆₀ to S _67, it detects the mark ratio other than 3/6.

FIG. 4 shows the mark ratios 0/6, 1/6, 2/6,
FIG. 14 is an electric circuit diagram for detecting 4/6, 5/6, 6/6 (however, 2/6, 4/6 are not included in the conversion pattern of FIG. 13).

In this figure, the mark ratios 0/6 and 1 shown in FIG.
/ 6 means AND circuit 25 (detects pattern (A) in Fig. 2)
Signal from the signal S ₅₀ and,, a signal and a signal S ₆₀ from the AND circuit 21 (detecting (C) pattern of FIG. 2), is detected by inputting the NAND circuit 22, respectively.

The mark ratios 5/6 and 6/6 shown in FIG.
Signals and signals from 26 (detecting the pattern (B) in FIG. 2)
The signal from the S ₅₇ and the AND circuit 23 (detecting the pattern (D) in FIG. 2) and the signal S ₆₇ are respectively connected to the NAND circuit 24.
Detected by inputting to.

The mark ratios 2/6 and 4/6 shown in FIG.
The ～2C, each signal S ₅₀ and the signal S _63, signal S ₅₁ and the signal
Detection is performed by inputting _S67 , signal _S53 and signal _S66 , signal _S54 and signal _S61 , signal _S56 and signal _S60, and signal _S57 and signal _S64 .

Then, such mark rates 0/6, 1/6, 2/6, 4/6, 5/6, 6/6 which are not in the conversion pattern shown in FIG. a NOR circuit 2E, it is detected by the NAND circuit 2F, and outputs the error detection signal S _8.

FIG. 5 is an electric circuit diagram for detecting the mark ratios 2/6 and 4/6 of the mark ratio detection circuit 2.

In this figure, the mark ratio shown in FIG.
Each signal S ₆₅ and the signal S ₆₆ to the AND circuit 2R～2U (of FIG. 2 (E) detecting a pattern), (detect (H) pattern of FIG. 2) signal S ₅₁ and the signal S _52, signal By inputting _S62 and signal _S64 (detecting the (F) pattern in FIG. 2) and signal _S53 and signal _S55 (detecting the (G) pattern in FIG. 2), (E) in FIG. ) To (H) are detected.

Then, the signals were detected by the NOR circuits 2G to 2J, respectively (E).
The pattern signals ~ (H), signal S _50, signal of FIG. 4
Individual patterns are detected by inputting S ₉₁ , signal S ₅₄ , and signal S ₆₀ , and these signals are detected by the NOR circuit 20.
By entering into, and outputs a detection signal S ₇₁ of the mark rate 2/6.

Moreover, the mark rate 4/6 shown in FIG. 2, to the AND circuit 2V～2Y, respectively signal S ₆₁ and the signal S ₆₂ (detecting a second view of (I) the pattern), the signal S ₆₃ and the signal S ₆₅ (detecting (J) pattern in FIG. 2), signal _S52 and signal _S54 (detecting (K) pattern in FIG. 2), signal _S55 and signal _S56 ((L) pattern in FIG. 2) Is detected), the second
Each pattern (I) to (L) in the figure is detected.

Then, the signals are detected by the NOR circuits 2K to 2N, respectively (I)
~ (L) pattern signal, signal _S57 , signal _S53 , signal S
₆₇ , the individual patterns are detected by inputting the signal S ₉₂ in FIG. 4, and by inputting these signals to the NOR circuit 2P, the mark ratio 4/6 is detected, and the NAND circuit 2
By inputting a detection signal of the detection signal S ₇₁ and the mark rate 4/6 of the mark rate 2/6 to Q, and outputs a detection signal S ₇₂ of the mark rates 2/6 and 4/6.

 FIG. 6 is an electric circuit diagram of the sign inversion circuit 3.

This circuit uses the fact that the individual bit patterns of the mark ratios 2/6 and 4/6 are the same pattern by inverting "1" and "0", so that the mark ratio 2/6 is detected. When the signal S ₇₁ is "0", the 6 bits from the 5B6B code signals S ₁₁ to S _16,
Outputs a positive logic signal by the inverter circuit 3N~3S and the select circuit 31 to 36, the detection signal S ₇₁ of the mark rate 2/6 is "1"
In this case, the mark ratio is set to 2/6 by outputting a signal of negative logic by the select circuits 31 to 36. In other words, patterns other than mark ratio 2/6 and 4/6 are 5B6B
Since the coding rule can be ignored without performing the inverse transformation, only the individual bit patterns at the mark rate of 2/6 need be detected here.

Detection of individual bit patterns in the mark rate 2/6 is detected depending on which position in the 5B6B code signals S ₁₁ to S ₁₆ of six bits "1" there are two. This is a NAND circuit 37～3H, and outputs a signal S ₂₁ to S ₂₅ converted by the NAND circuit 3I~3M by the detected pattern. Also, only 11 out of 12 patterns with a mark ratio of 2/6 are detected. When “000101” is not detected, all the NAND circuits 37 to 3H output “1”, and the NAND circuits 37 to 3H output “1”. This is because 3I to 3M output "0" and need not be detected.

Figure 7 is an electrical circuit diagram of the select circuit 4, as shown in this figure, the select circuit 41 to 45, control signal S ₇₂
(The detection signals of the mark ratios 2/6 and 4/6) and the control signal S ₈ (error detection signal). Where the control signal
When S ₇₂ is “1”, the signal S that has been subjected to the 5B6B
₂₁ Select-signal S _25, the control signal when S ₈ is "1", selects the error signal "10101", the control signal S ₈ and S ₇₂
There When both are "0", i.e. Ma - when click rate is 3/6, by selecting signals S ₁₁ ~ signal S _15, and outputs a signal S ₃₁ ~ signal S _35.

Next, the relationship between input and output will be described throughout FIGS. 1 to 7. FIG.

Signals S ₅₀ ~ signal S ₅₇ in FIG. 3 corresponds to the 8-bit signals decoded indicated by signal S ₅ of FIG. 1, the signal S ₆₀ ~ signal S ₆₇ in FIG. 3, the first corresponding to 8-bit signals decoded indicated by signal S ₆ of FIG.

The fourth signal S ₅₀ ~ signal S ₅₇ in the figure, signals S ₅₀ ~ signal S ₅₇ shown in Figure 3 are inputted respectively, signals S in FIG. 4
_The signals S60 to _S67 shown in FIG. 3 are input to the signals ₆₀ to _S67 , respectively. The error detection signal shown in FIG.
S ₈ is a signal S ₈ shown in Figure 1.

The fifth signal S ₅₀ ~ signal S ₅₇ in the figure, signals S ₅₀ ~ signal S ₅₇ shown in Figure 3 are inputted respectively, signals S in FIG. 5
From ₆₀ to signal S _67, signals S ₆₀ to signal S ₆₇ shown in Figure 3 is inputted, the signal S ₉₁ and the signal S ₉₂ in Fig. 5,
Signal S ₉₁ and the signal S ₉₂ shown in FIG. 4 are respectively input.

Signal S ₇₁ in FIG. 5, of the signal S ₇ in FIG. 1, the signal in FIG. 5 is a signal which is input to the code inverse conversion circuit 3 S
_72, of the signal S ₇ in FIG. 1, a signal input to the select circuit 4.

The sixth signal S ₁₁ ~ signal S ₁₆ in the figure, the signal S ₁₁ shown in FIG. 3 (D ₁₎ ~ signal S ₁₆ (D ₆₎ is input. This signal S
₁₁ to the signal S ₁₆ corresponds to a 6-bit signal shown by the signal of FIG. 1 _{S 1 (D 1 ~D 6)} . Further, in the sixth signal S ₇₁ in the figure, the signal S ₇₁ shown in FIG. 5 is input.

The signals S ₁₁ ~ signal S ₁₅ in FIG. 7, the signal S ₁₁ shown in FIG. 3 (D ₁₎ ~ signal S ₁₆ upper five bits of the signal of the (D ₆₎
S ₁₁ (D ₁ ) to S ₁₅ (D ₅ ) are input. Further, in the seventh signal S ₂₁ ~ signal S ₂₅ in the figure, signals S ₂₁ ~ shown in Figure 6
Signal S ₂₅ is input. The signals S ₂₁ ~ signal S _25, the first
Corresponding to the 5-bit signal shown by the signal S ₂ in FIG. The seventh signal S ₇₂ in the figure, the signal S ₇₂ shown in FIG. 5 is input to the signal S ₈ in FIG. 7, the error detection signal S ₈ shown in FIG. 4
Is entered. Signals S ₃₁ ~ signal S ₃₅ in FIG. 7 corresponds to the 5-bit signal shown by the signal S ₃ in Figure 1.

Next, a description will be given of which circuit detects each bit pattern shown in FIG.

First, the detection of the mark ratios 0/6 and 1/6 shown in FIG.
This is performed by detecting the 6-bit pattern shown in (a) and the 6-bit pattern shown in (b) in the figure. That is, the upper three bits D ₁ , D ₂ , D ₃ are “000” and the lower three bits D ₄ ,
If D ₅ and D ₆ are any of “001”, “010” or “100” (the 6-bit pattern is indicated by (A) in the figure), the upper 3 bits D ₁ , D ₂ and D ₃ is “000”, “001”, “010”, “100”
In this case, the detection is performed by detecting the case where the lower three bits D ₄ , D ₅ , D ₆ are “000” (the pattern of these 6 bits is indicated by (b) in the figure).

Similarly, the detection of the mark ratios 5/6 and 6/6 shown in FIG. 2 is performed by detecting the 6-bit patterns shown in (c) and (d) in FIG. Mark rate 2/6 is detected by (e), (f), (g),
The detection is performed by detecting each of the 6-bit patterns shown in (h), and the mark ratio 4/6 shown in FIG.
This is performed by detecting the 6-bit patterns indicated by (l), (nu), (lu), and (ヲ) in the figure, respectively.

The detection of the mark ratios 2/6 and 4/6 shown in FIG. 2, that is, the detection of the mark ratios 2/6 and 4/6 that are not in the conversion pattern of FIG. Medium (wa),
This is performed by detecting the 6-bit patterns indicated by (f), (yo), (ta), (d), and (so), respectively.

FIGS. 3 to 5 show bit patterns of 3 bits decoded on the respective lines. In connection with the above, FIGS. 4 and 5 show FIGS.
Gate circuits for detecting the 6-bit pattern shown in (G) are shown in (A) to (G), respectively.

As for the sign inversion circuit 3 shown in FIG. 6 and the select circuit 4 shown in FIG. 7, a conventionally known circuit can be applied, so that the detailed description is omitted.

Next, FIGS. 8 to 12 show another embodiment of the present invention.

FIG. 8 is an explanatory diagram showing the basic structure of a 5B6B coding rule inverse transform circuit as another embodiment of the present invention.

As shown in FIG. 8, the 5B6B coding rule inversion circuit in this embodiment comprises a first mark rate detection circuit 51 for detecting the mark rates of the upper 3 bits of D1 to D3, and a lower 3 bits of D4 to D6. A second mark ratio detection circuit 52 for detecting a mark ratio;
From the mark rates detected by the second mark rate detection circuits 51 and 52, D
A 6-bit mark ratio determination circuit 53 for determining a 6-bit mark ratio of 1 to D6 is provided. In this embodiment,
Only a circuit portion for detecting a 6-bit mark rate is shown.

That is, in this embodiment, as in the above-described embodiment, the 6-bit 5B6B code signal of D1 to D6 is divided into three bits, but without using the 3: 8 decoder, for each three bits, OR (hereinafter referred to as OR), AND (hereinafter AN)
D)) and exclusive OR (hereinafter referred to as EOR), and the respective mark ratios are detected.

The circuit diagram of this logic is shown in FIG. 9 and the logic values are shown in FIG. From the output value of the logic circuit shown in FIG. 9, a 3-bit mark rate as shown in FIG. 10 can be detected as follows.

When the value of the OR circuit is “0”, the mark rate is 0/3. When the value of the OR circuit is “1”, the value of the AND circuit is “0”, and the value of the EOR circuit is “1”, the mark rate is 1 / 3 Mark ratio when OR circuit value is “1”, AND circuit value is “0”, and EOR circuit value is “0”. Mark when the AND circuit value is “1”. As the rate 3/3, the mark rate of each 3 bits is detected, and the combination of both results is used to determine the mark rate.
A 6-bit mark rate as shown in FIG. 11 is obtained.

FIG. 12 is an electrical circuit diagram of the 5B6B coding rule inverse transform as another embodiment shown in FIG.

In the figure, the circuits enclosed by broken lines correspond to the circuits shown in FIG. 8, respectively.
Noah (hereinafter referred to as NOR) circuit 51a, AND circuit 51b, EOR circuit 5
1c, a NOR circuit 51d, and a NOR circuit 51e. Similarly, as the second mark rate detection circuit 52, the NOR circuit 52a, the AND circuit 52b,
The EOR circuit 52c, the NOR circuit 52d, and the NOR circuit 52e are used.

Further, as the 6-bit mark rate determination circuit 53, AND circuits 61 to 6C and OR circuits 53a, 53b, 53c, 53d are used.

In this way, the 6-bit 5B6B code signal is
Bit and lower 3 bits, and from those patterns
By detecting the mark rate of the 5B6B code signal, the number of detection patterns can be reduced, and the circuit scale can be reduced as compared with the related art.

[Effects of the Invention] According to the present invention, a 6-bit signal subjected to 5B6B coding rule conversion is divided into upper 3 bits and lower 3 bits, and a 6-bit mark rate is detected from those patterns.
Since the inverse transformation of the 6B coding rule is performed, the number of detection patterns can be reduced, and the circuit scale and the number of redundant circuits can be reduced.

In addition, since the circuit is simplified, the manufacturing cost is reduced as compared with the related art, and elementary errors such as input errors in the circuit diagram are reduced. Further, with simplification of the circuit, cost reduction such as reduction of power consumption can be achieved.

[Brief description of the drawings]

1 to 7 show an embodiment of the present invention. FIG. 1 is an explanatory diagram showing a basic structure, FIG. 2 to FIG. 2 are explanatory diagrams showing a mark ratio in each bit pattern, and FIG. 3: 8
FIG. 4 is a circuit diagram of a decoder, FIG. 4 is an electric circuit diagram for detecting a mark ratio 0/6, 1/6, 2/6, 4/6, 5/6, 6/6 of a mark ratio detection circuit, and FIG. The figure is an electric circuit diagram for detecting the mark ratio 2/6, 4/6 of the mark ratio detection circuit, FIG. 6 is an electric circuit diagram of the sign inversion circuit, and FIG. 7 is an electric circuit diagram of the select circuit. .
8 to 12 show another embodiment of the present invention. FIG. 8 is an explanatory diagram showing a basic structure, FIG. 9 is a logic circuit diagram, and FIG.
FIG. 10 is an explanatory diagram showing logical values of the logical circuit shown in FIG. 9,
FIG. 11 is an explanatory diagram showing an extension pattern to a 6-bit mark rate, and FIG. 12 is an electric circuit diagram. FIG. 13 is an explanatory diagram showing a 5B6B coding rule conversion pattern, and FIG. 14 is a conventional 5B6B coding rule conversion circuit. 1a ... first 3: 8 decoder, 1b ... second 3: 8 decoder,
2... Mark ratio detection circuit, 3... Sign reverse conversion circuit, 4.
... Select circuit, 51 ... First mark ratio detection circuit, 52 ...
Second mark ratio detection circuit, 53... 6-bit mark ratio determination circuit.

 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-61-95649 (JP, A) JP-A-61-145934 (JP, A) JP-B1-151094 (JP, B2) JPB-B3- 81334 (JP, B2)

Claims (2)

(57) [Claims] 1. A first method of dividing a signal consisting of a series of bits converted into a 5B6B code rule into 6 bits, and generating signals of 8 patterns from upper 3 bits of the divided 6 bits.
A decoder (1a) and the lower 3 bits of the divided 6 bits
A second decoder (1b) for generating eight patterns of signals from the bits, and a mark for detecting the divided 6-bit mark ratio from the eight patterns of signals from the first and second decoders (1a) and (1b), respectively. 5B according to the mark ratio detected by the mark detection circuit (2) and the mark ratio detection circuit (2).
A code inverse conversion circuit (3) for performing an inverse conversion of the 6B code rule and converting the divided 6 bits into a 5-bit signal; and the code inverse conversion according to a mark rate detected by a mark rate detection circuit (2). A selection circuit (4) for selecting and outputting one of a 5-bit signal inversely converted by the circuit (3), an upper 5-bit signal of the divided 6 bits, or an error signal; 5B6B coding rule inverse transformation circuit. 2. A first mark rate detection circuit (51) for dividing a signal consisting of a series of bits subjected to 5B6B code rule conversion into 6 bits and detecting a mark rate of upper 3 bits for the 6 bits. The lower 6 bits of the divided 6 bits
The second mark rate detection circuit (5
2) a 6-bit mark rate determination circuit for determining the divided 6-bit mark rate according to the mark rates detected by the first mark rate detection circuit (51) and the second mark rate detection circuit (52) 5B6B code rule inverse conversion circuit comprising (53).