JPH04176233A - 5b6b code rule inverse conversion circuit - Google Patents

Abstract

PURPOSE:To reduce a detection pattern number and to decrease the circuit scale and number of redundant circuits by dividing a 6 bit signal subject to 5B6B code rule conversion into high-order 3 bits and low-order 3 bits, detecting a mark rate in 6 bits from the pattern and applying inversion of the 5B6B code rule. CONSTITUTION:A signal subject to 5B6B code rule is divided to 6 bits each, an 8-pattern signal is generated from a signal of high-order 3 bit in the 6 bits and an 8-pattern signal is generated from a signal of low-order 3 bit in the 6 bits respectively by 1st and 2nd decoders 1a, 1b, and a mark rate of the divided 6 bits is detected from each 8-pattern signal by a mark rate detection circuit 2. Then any of the 5-bit signal subject to inversely conversion by a code inverse conversion circuit 3, the high-order 5-bit signal in the divided 6 bits and an error signal is selected and outputted in response to the mark rate. Thus, the number of detected patterns is reduced and the circuit scale is reduced more than that of a conventional system.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a 5B6B coding rule inverse conversion circuit that is mainly used for digital transmission and inversely converts a 6-bit signal subjected to 5B6B coding rule conversion into an original 5-bit signal. When inverting the rules, instead of detecting all 6-bit patterns, the pattern is divided into the upper 3 bits and lower 3 bits, and the 6-bit mark rate is detected from these patterns, thereby reducing the number of detected patterns. The aim is to simplify the circuit by dividing the signal consisting of a series of bits converted to the 5B6B coding rule into 6 bits each, and generating 8 patterns of signals from 3 bits of the 6 divided bits. a mark rate detection circuit that detects the divided 6-bit mark rate from each of the eight patterns of signals from the first and second decoders; and a mark rate detected by the mark rate detection circuit. a code inverse conversion circuit that performs inverse conversion of the 5B6B code rule in accordance with the mark rate detected by the mark rate detection circuit; It is configured to include a select circuit that selects and outputs one of the converted 5-bit signal, the upper 5-bit signal of the divided 6 bits, or the error signal.

[Industrial Application Field] This invention is mainly used for digital transmission, and is
The present invention relates to a 5B6B sign rule inverse conversion circuit that inversely converts a 6-bit signal subjected to B sign rule conversion into an original 5-hint signal.

[Prior Art] Generally, regenerative repeaters used in digital transmission employ a self-timing method that extracts a timing wave from the received pulse train itself.

In such a timing extraction method, the input code sequence is “
In the case of consecutive zero codes such as "000.", timing information may be lost on the transmission path.

Therefore, in digital transmission, in order to avoid such loss of timing information, 5B6 is used during data transmission.
B code rule conversion is performed to suppress consecutive zero codes. Here, 5B6B code rule conversion means dividing the digital signal string into 5 bits each, and converting the 5B6B code into 5B bits as shown in Figure 13.
This 5-bit signal is converted into a 6-bit 5B6B code signal according to a 6B code rule conversion pattern.

At the time of reception, the receiver divides the received digital signal string into 6 bits each, performs inverse conversion using the 5B6B coding rule, and obtains the original 5-bit signal.

FIG. 14 shows a conventional 5B6B sign rule inverse conversion circuit.

As shown in the figure, the conventional 5B6B code rule inverse conversion circuit first detects the mark rate of the 6-bit signal to be inversely converted, and then performs the 5B6B code rule inverse conversion accordingly. The mark rate here is the ratio of "on" bits among the 6 pits, and in the figure,
/6.2/6 is displayed as a fraction.

In other words, the conventional 5B6B sign rule inverse conversion circuit has the 13th
Mark rate that is not in the conversion pattern in the figure, that is, mark rate 0/
6, 1/6.2/6.4/6.5/6 or 6/6 (however, the mark rate 2/6.4/6 is not in the conversion pattern in Figure 13), and signal 38 when
The first detection circuit 11a that outputs B and the mark rate in the conversion pattern of FIG. 13, that is, the mark rate 2/6.3/6
or 476, outputs a signal 5B11 when the mark rate is 276 or 476, and outputs a signal S87 when the mark rate is 376;
When the signal See is output from the second detection circuit ttb, Di
- A sign inversion circuit 2 which inversely converts the 6-bit signal Sat of D6 using the 5B6B sign rule and outputs it as a 5-bit signal S82; When S87 is output, the select circuit I3 selects and outputs the signal 5B5 (5-bit signal from DI to D5) as the signal S83, and the first detection circuit 11a normally outputs the signal S83 as the signal S84. When signal S88 is output from
ot 01'' as a signal Ssa.

In this way, the conventional 5B6B code rule inverse conversion circuit detects the mark rate of the 6-bit 5B6B code signal,
If the mark rate is 2/6.3/6 or 476, then the 5B6B sign rule inverse conversion is performed based on the conversion pattern of FIG. 13, and the mark rate is O/6.1/6.2/6. 4
/6.5/6 or 676 (however, mark rate 2/6.4/
6, which is not in the conversion pattern shown in FIG. 13), it is converted into a 5-bit one word "10101".

[Problems to be Solved by the Invention] However, in such a conventional 5B6B code rule inversion circuit, when each mark rate is detected by the first detection circuit 11a and the second detection circuit 11b, a 6-bit signal is used. Since all patterns (64 patterns) are detected, the circuit scale becomes large and there is a problem that the circuit includes many redundant circuits.

This invention was made in consideration of these circumstances, and therefore, when inverting the 5B6B code rule, instead of detecting the pattern of all 6 bits, the pattern is divided into the upper 3 bits and the lower 3 bits, and the patterns are detected. The present invention provides a 5B6B code rule inverse conversion circuit in which the circuit is simplified by detecting the mark rate of 6 hints from the pattern and reducing the number of -7=detected patterns.

[Means for Solving the Problems] The invention according to claim 1 of the present application divides a signal consisting of a series of bits subjected to 5B6B code full conversion into 6 bits each, and starts from the upper 3 bits of the divided 6 bits. A first decoder la that generates eight patterns of signals, a second decoder 1b that generates eight patterns of signals from the lower three bits of the divided six bits, and each of the first and second decoders 1a and 1b. A mark rate detection circuit 2 detects the mark rate of the divided 6 bits from the 8 pattern signals, and performs inverse conversion of the 5B6B code rule according to the mark rate detected by the mark rate detection circuit 2 to detect the divided 6 bits.
A code inversion circuit 3 that converts bits into a 5-bit signal, a 5-bit signal inversely converted by the code inversion circuit 3 according to the mark rate detected by the mark rate detection circuit 2, and the divided 6 bits. This is a 5B6B code rule inverse conversion circuit comprising a select circuit 4 that selects and outputs one of the upper five bit signals or the error signal.

Further, the invention according to claim 2 of the present application provides a first mark rate that divides a signal consisting of a series of bits subjected to 5B6B coding rule conversion into 6 bits each, and detects the mark rate of the upper 3 bits for the divided 6 bits. a detection circuit 51, a second mark rate detection circuit 52 that detects the mark rate of the lower three bits for the divided six hinoto, and a first mark rate detection circuit 5.
1 and a second mark rate detection circuit 52;
This is a B sign rule inverse conversion circuit.

[Operation] According to the invention according to claim 1 of the present application, a signal subjected to 5B6B coding rule conversion is divided into 6 bits each, and the first and second bits are divided into 6 bits.
The decoders 1a and 1b generate 8 patterns of signals from the upper 3 bits of the 6 bits, and 8 patterns of signals from the lower 3 bits, and the mark rate detection circuit 2 generates 8 patterns for each of the 8 patterns. The divided 6-bit mark rate is detected from the signal.

Then, according to the mark rate, the select circuit 4 selects one of the 5-bit signal inversely converted by the code inverse conversion circuit 3, the upper 5-bit signal of the divided 6 bits, or the error signal. is selected and output.

Therefore, the 6-bit signal is divided into the upper 3 bits and the lower 3 bits, and the 6-bit mark rate is detected from these patterns, so the number of detection patterns can be reduced, and thereby The circuit scale can be reduced compared to conventional methods.

Further, according to the invention according to claim 2 of the present application, the signal subjected to the 5B6B code conversion is divided into 6 bits each, and the mark rate of the upper 3 bits of the divided 6 bits is determined by the first mark rate raising circuit 51. Or the second mark rate detection circuit 52
Accordingly, the mark rate of the lower 3 bits of the divided 6 bits is detected.

Then, the 6-bit mark rate determination circuit 53 determines the divided 6-bit mark rate according to the mark rates detected by the first mark rate detection circuit 51 and the second mark rate detection circuit 52.

Therefore, a 6-bit signal consists of the upper 3 bits and the lower 3 bits.
Since the mark rate of 6 bits is determined from these mark rates, the number of detection patterns can be reduced, and the circuit scale can thereby be made smaller than before.

[Example] Hereinafter, the present invention will be described in detail based on the example shown in the drawings. Note that this invention is not limited to this.

FIG. 1 shows 5.5 as an embodiment of the present invention. B6B code I
11 is a configuration explanatory diagram showing the basic configuration of a No. 11 inverse conversion circuit. FIG.

In FIG. 1, 1a and 1b are the first and second 3LI
NE to 8L+NE Decoder/Demul
tiplexer (hereinafter abbreviated as 38 decoder),
2 is a mark rate detection circuit, 3 is a sign inversion circuit, and 4 is a selection circuit.

The first 38 decoder 1a receives a 6-bit signal S, (I)
8 from the upper 3 bits (Di to D3) of
The second 38 decoder lb generates a pattern conversion signal S5, and converts the lower 3 bits (D4 to D6) of the signal S1.
8 patterns of conversion signals SQ are generated from the above.

The mark rate detection circuit 2 receives a conversion signal S5 of 8 patterns x 2.
．． From SL+, the mark rate in the 5B6B code rule conversion pattern shown in FIG. 13, that is, the mark rate 276 or 4
When it detects 76, it outputs a signal S7 and detects a mark rate that is not in the conversion pattern of FIG. 13, that is, a mark rate of 0/6,
When detecting 1/6.2/6, 4/6, 5/6, or 676 (however, the mark rate 2/6.4/6 is not in the conversion pattern of Fig. 13), outputs signal S8. .

The sign inverse conversion circuit 3 receives the signal S7 from the mark rate detection circuit 2.
is output, the signal S1 is inversely converted to the 5B6B sign rule based on the conversion pattern shown in FIG. 13, and the 5-bit signal S
Output as 2.

When the mark rate detection circuit 2 outputs the signal S7, the select circuit 4 selects and outputs the signal S2 as it is as the signal S3, and when the mark rate detection circuit 2 outputs the signal S8, the select circuit 4 outputs the signal "10101" as the signal. S3 is selected and output, and when both the signal S7 and the signal S8 are not output from the mark rate detection circuit 2, it is assumed that the mark rate is 376, and the signal S
, (5-bit signals up to DI-D5) are selectively output as signal S.

In this way, in this embodiment, 6 bits of 5B6B
Divide the code signal S1 into 3 bits, the first and second 38 bits.
16 patterns for decoders la and Ib (8 patterns x 2)
The converted signal S5. generate S. Then, the mark rate detection circuit 2 detects all patterns (44 patterns) other than the mark rate 376, and detects the signal S8 (error signal) when the conversion pattern shown in FIG.
If signal S7 is detected, signal S2 is generated; if signal S8 is detected, signal "10101" is generated; and if both signal S7 and signal S8 are not detected, signal S7 is generated. S4 is selected by the select circuit 4, respectively, and a 5-bit signal S3 is output.

As a result, in the mark rate detection circuit 2, the mark rate 3
There is no need to detect 76. Also, the first and second 3
By using 8 decoders], a, and Ib, mark rate detection can be performed simply by combinations of numbers as shown in (1) to (2) in FIG.

Note that the mark rate detection circuit 2 performs 3-bit units (DI~
Since the mark rate is detected using each 3-bit signal (D3 and D4 to D6), overlapping patterns are used, as shown in patterns (A) to (L) of the mark rate calculation method for each bit pattern shown in Figure 2. A pattern emerges. This means that when the signals D1 to D3 are "000", the D4-D6t7) signal is pattern (A) ("001").

If the DI-D3 signal is either (H) pattern (“001” or “010”), the mark rate is 176, and if the DI-D3 signal is either (H) pattern (“001” or “010”), ~
If the signal of D6 is one of the patterns (A),
This shows that the mark rate is 276.

In this way, the mark rate detection circuit 2 detects D1 to D1 when pattern (A) is detected, as shown by
If the D3 signal is “000”, the mark rate is 176,
In the case of the (H) pattern, the mark rate is 276, so the circuit configuration can be simplified.

In the sign inverse conversion circuit 3, the mark rate is 2/6, 4/
6 (the pattern in the conversion pattern of FIG. 13), the output signal S2 from the sign inversion circuit 3 becomes the output signal S3 as it is. Since the mark rates 2/4 and 476 are the same signal if inverted, the sign inverse conversion circuit 3 inputs the signal Sl as is when detecting the mark rate 2/6, and inputs the signal S when the mark rate is other than 276.

Conversion is performed by inverting and inputting. In addition, when performing inverse transformation, the inverse transformation is performed by detecting a pattern with a mark rate of 276, but since the mark rate of 276 has only two "l"s, the inverse transformation is performed depending on the position of "1". It has a circuit configuration that performs this.

In select circuit 4, instead of using 10 conventional 2=1 select circuits, 5 31 select circuits are used.
I try to use it. This select circuit 4 is required for all 5 bits of the output signal S3, and conventionally a two-stage select circuit was used, resulting in a large circuit size, but by using a 3:1 select circuit,
The circuit configuration is such that it is possible to reduce the circuit scale and reduce redundant circuits.

Figures 3 to 7 show 5B6B as an embodiment of this invention.
FIG. 2 is an electrical circuit diagram of sign rule inversion.

FIG. 3 is a circuit diagram of the first and second 38 decoders La and 1b, and as shown in the figure, 5 bits of 6 bits (DL-D6)
B6B code signal 5ll-3il+, first and second 3:
16 patterns (8 patterns x 2) of signals 55o-857 and S using 8 decoders Ia and lb. ~S 117
Convert to Then, the converted signal S 5o−S 57
and S 6 (detect mark rates other than 376 from 1-3117).

Figure 4 shows the mark rate of mark rate detection circuit 2: 0/6.1/6.
．． 2/6.4/6.5/6.6/6 (However, 2/6,
476 is an electric circuit diagram for detecting a pattern (not included in the conversion pattern of FIG. 13).

In this figure, the mark rates 076 and 176 shown in ■ in FIG.
(Detection of pattern (C) in Figure 2) and signal S
. 0 is detected by inputting each to a NAND circuit 22.

The mark rates 576 and 676 shown in ■ in FIG. 2 are the signal from the AND circuit 26 (detecting the pattern (B) in FIG.
) pattern detection) and the signal S87 are respectively input to the NAND circuit 24 for detection.

The mark rates 276 and 476 shown in ■ in FIG. 2 are the signals S5o, the signal se3, the signal S5+, and the signal S, respectively, in the NOR circuits 27 to 2C. 7. Detection is performed by inputting the signal S53 and the signal S8e, the signal S5a and the signal S Ill, the signal 35G and the signal S so, and the signal S, 7 and the signal Sea, and the conversion shown in FIG. Mark rate not in pattern 0/6, 1/6.2/6.4/8.
5/6.6/6 is detected as an error by the NOR circuit 2D, the NOR circuit 2E, and the NAND circuit 2F, and outputs an error detection signal S8.

FIG. 5 shows mark rates 276 and 47 of mark rate detection circuit 2.
FIG. 6 is an electrical circuit diagram for detecting 6.

In this figure, the mark rate 276 shown in ■ in FIG.
l and signal S5. (detects pattern (H) in Figure 2), inputs signal S82 and signal 564 (detects pattern (P) in Figure 2), and inputs signal S53 and signal 555 (detects pattern (G) in Figure 2) By doing so, (E) to ( in Fig. 2) are obtained.
Detect each pattern of H).

Then, each of the NOR circuits 2G to 2J was detected (E
) to (H'I pattern signal, signal s5o, signal ■ in FIG. , and outputs a detection signal S7+ with a mark rate of 276.

In addition, the mark rate 476 shown in ■ in FIG.
(Detection of pattern (I) in Fig. 2), signals S, 3 and signal 5
65 (detected pattern (J) in Figure 2), signal S 52
By inputting the signal 554 (detecting the (K) pattern in FIG. 2), the signal S 55 and the signal 556 (detecting the (L) pattern in FIG. 2), the signals (r) to (L) in FIG. ) to detect each pattern.

Then, in the NOR circuit 2, ~2N were detected (r
) to (L) pattern signals, signal S57, signal S53
, the signal 5117, and the signal ■ in FIG. 276 detection signal S7
By inputting the detection signals of + and mark rate 4/6, detection signals S7° of mark rates 276 and 476 are output.

FIG. 6 is an electrical circuit diagram of the sign inversion circuit 3.

In this circuit, the individual bit patterns of mark rates 276 and 476 are the same pattern if "1" and "0" are inverted, so that the detection signal S71 of mark rate 276 is "0". ”, from the 6-bit 5th 6B code signal S l l-818, the inverter circuit 3N~
3S and the select circuits 31 to 36 output a positive logic signal, and when the mark rate 276 detection signal S71 is "l", the select circuits 31 to 36 output a negative logic signal, thereby increasing the mark rate 276. I'm trying to make it happen. In other words, since patterns other than mark rates 2/6 and 4/6 can be ignored without being inversely converted to the 5B6B code I11, only individual hint patterns at a mark rate of 276 need be detected here.

Detection of individual bit patterns at a mark rate of 276 is based on where two °°1'' are located in the 6-bit 5B6B code signal 5ll-818. , the signal S21 is converted by the NAND circuits 3-3M according to the detected pattern.
'-S25 is output.

Also, out of 12 patterns with a mark rate of 2/6, only 11 are detected because when "000101" is not detected, all NAND circuits 37 to 3H output "1", and the NAND circuit This is because the signals 3.about.3M output "0" and therefore do not need to be detected.

FIG. 7 is an electrical circuit diagram of the select circuit 4, and as shown in this figure, each select circuit 41 to 45 receives a control signal 5.
72 (mark rate detection signal of 276 and 476) and control signal 5Il (error detection signal). Here, when the control signal S is 72 or "l", 5B6
Select the signals 821 to S25 that have been inversely converted to the B sign rule, and when the control signal S8 is "1", the error signal "1" is output.
0101'' is selected and control signals S8 and S?'2 are both "0", signals 331 to 52K are output by selecting signals S11 to S15.

Next, embodiments of the pond of this invention are shown in FIGS. 8 to 12.

FIG. 8 is a configuration explanatory diagram showing the basic configuration of a 5B6B code rule inversion circuit as another embodiment of the present invention.

As shown in FIG. 8, the 5-day 6B code rule inverse conversion circuit in this embodiment includes a first mark rate detection circuit 51 that detects the mark rate of the upper three bits of D1 to D3, and a first mark rate detection circuit 51 that detects the mark rate of the upper three bits of D1 to D3, and a second mark rate detection circuit 52 for detecting the mark rate of bits; A 6-bit mark rate determination circuit 53 is provided that determines the mark rate of 6 bits D1 to D6 from the mark rate detected by the second mark rate detection circuits 51 and 52.

In this embodiment, only the circuit portion for detecting the mark rate of 6 hinoto is shown.

That is, in this embodiment, similarly to the previous embodiment, the 6-bit 5B6B code signal of D1 to D6 is divided into 3 bits each, but the 38 decoder is not used.
For each 3 bits, OR (hereinafter referred to as OR), AND (hereinafter referred to as AND), and exclude or (hereinafter referred to as FOR) logic is performed to detect each mark rate.

A circuit diagram of this logic is shown in FIG. 9, and logic values are shown in FIG. 10. From the output value of the logic circuit shown in FIG. 9, the 3-bit mark rate as shown in FIG. 10 can be detected as follows.

■When the value of the OR circuit is “0”, the mark rate is 0/3 ■The value of the OR circuit is “l”, the value of the AND circuit is “0”, and the FOR
When the value of the circuit is “1”, the mark rate is 1/3 ■When the value of the OR circuit is “l”, the value of the AND circuit is “0”, and the value of the FOR circuit is “0”, the mark rate is 2 /3 ■When the value of the AND circuit is 1”, the mark rate is 3/3,
The mark rate of each 3 bits is detected, and from the combination of both results, the mark rate of 6 bits as shown in FIG. 11 is determined.

FIG. 12 shows 5B6B as another embodiment shown in FIG.
FIG. 3 is an electrical circuit diagram of code III inversion.

In the figure, the circuits surrounded by broken lines correspond to the circuits shown in FIG. 8, and the first mark rate detection circuit 51 is as follows.
NOR (hereinafter referred to as NOR) circuit 5Ia, AND circuit 5
l b, EOR circuit 51c, NOR circuit 51d, and N
Even if the second mark rate detection circuit 52 uses the OR circuit 51e, the same <N.

R circuit 52a, AND circuit 52b, SEOR circuit 52c,
, a NOR circuit 52d, and a NOR circuit 52e.

As the 6-bit mark rate judgment circuit 53, AN
D circuits 61-60 and OR circuits 53a, 53b, 53c
, 53d are used.

In this way, by dividing the 6-bit 5B6B code signal into the upper 3 bits and lower 3 bits and detecting the mark rate of the 5B6B code signal from these patterns,
By reducing the number of detection patterns, the circuit scale can be made smaller than before.

[Effects of the Invention] According to this invention, a 6-pit signal subjected to 5B6B code rule conversion is divided into upper 3 bits and lower 3 bits, the mark rate of 6 bits is detected from these patterns, and then the 5B6B code is converted into Since the inverse transformation of the rule is performed, it is possible to reduce the number of detected patterns, thereby reducing the circuit scale and the number of redundant circuits.

Furthermore, since the circuit is simplified, manufacturing costs are reduced compared to the conventional method, and elementary mistakes such as mistakes in inputting circuit diagrams are reduced. Furthermore, with the simplification of the circuit, cost reductions such as reduction in power consumption can be achieved.

[Brief explanation of the drawing]

1 to 7 show an embodiment of the present invention, in which FIG. 1 is an explanatory diagram showing the basic configuration, ■ to ■ in FIG. 2 are explanatory diagrams showing mark rates in each bit pattern, and The figure is 38
The circuit diagram of the decoder, FIG. 4, shows the mark rate detection circuit with a mark rate of 0/6. l/6, 2/6.4/6.5/6.6/6
Figure 5 is an electric circuit diagram for detecting the mark rate 2/6.4/6 of the mark rate detection circuit. Figure 6 is an electric circuit diagram of the sign inversion circuit. FIG. 7 is an electrical circuit diagram of the select circuit. 8 to 12 show embodiments of the pond of this invention, FIG. 8 is a configuration explanatory diagram showing the basic configuration, FIG. 9 is a logic circuit diagram, and FIG. 10 is the logic circuit shown in FIG. 9. FIG. 11 is an explanatory diagram showing an expansion pattern to a mark rate of 6 pits, and FIG. 12 is an electric circuit diagram. FIG. 13 is an explanatory diagram showing a 5B6B code rule conversion pattern, and FIG. 14 is a conventional 5B6B code rule inverse conversion circuit. ■a - First 3:8 decoder, tb - Second 3:8 decoder, 2 - Mark rate detection circuit, 3... Sign inverse conversion circuit, 4
Select circuit, 51 - first mark rate detection circuit, 52 - second mark rate detection circuit, 53 ... 6-bit mark rate determination circuit. 261C) - one bite

Claims (1)

[Claims] [1] A first method in which a signal consisting of a series of bits subjected to 5B6B coding rule conversion is divided into 6 bits each, and 8 patterns of signals are generated from the upper 3 bits of the divided 6 bits.
a decoder (1a), a second decoder (1b) that generates eight patterns of signals from the lower three bits of the divided six bits, and first and second decoders (1a) and (1
a mark rate detection circuit (2) that detects the mark rate of the divided 6 bits from each of the 8 patterns of signals from b);
a code inverse conversion circuit (3) that performs inverse conversion of the 5B6B code rule according to the mark rate detected by the mark rate detection circuit (2) and converts the divided 6 bits into a 5 bit signal;
and a 5-bit signal inversely converted by the code inverse conversion circuit (3) according to the mark rate detected by the mark rate detection circuit (2), a signal of the upper 5 bits of the divided 6 bits, or a 5B6B sign rule inverse conversion circuit comprising a select circuit (4) that selects and outputs one of the error signals. [2] A first mark rate detection circuit (51) that divides a signal consisting of a series of bits subjected to 5B6B coding rule conversion into 6 bits each and detects the mark rate of the upper 3 bits of the divided 6 bits; A second mark rate detection circuit detects the mark rate of the lower 3 bits of the divided 6 bits (
52), and a 6-bit mark rate determination circuit that determines the mark rate of the divided 6 bits according to the mark rate detected by the first mark rate detection circuit (51) and the second mark rate detection circuit (52). (53) A 5B6B sign rule inverse conversion circuit.