JPS62180611A - Code conversion transmission system - Google Patents

Abstract

PURPOSE:To decrease a synchronization restorating time and to simplify the circuit constitution by assigning a bit not allocated with the information of an input data signal in an n-bit code word to a synchronizing frame pattern and using the said frame pattern so as to take the frame synchronization. CONSTITUTION:In the system converting an input data signal of plural (m) bits into a code word of plural (n) bits (m<n) and sending the word, a bit not allocated with the information of the input data signal in the n-bit code word is assigned to the synchronizing frame pattern at the sending side. The frame pattern is detected at the reception side to establish the block and frame synchronization. Although (2<n>-2<m>)-set of n-bit pattern is not allocated with the information of the input data signal in the mBnB code (m<n) in general, the information is assigned as the frame synchronizing pattern in this case. Thus, the frame synchronizing circuit is simplified and the synchronization restoring time is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention is applied to digital code communication. In particular, it relates to a method for achieving block synchronization and frame synchronization between the transmitting side and the receiving side.

Here, mBnB code conversion refers to converting a plurality of m-bit input data signals into a plurality of n-bit code words (m<n).

〔overview〕

In the mBnB code conversion transmission system, the present invention allocates bits of an n-bit code word to which information of an input data signal is not allocated to a frame pattern for synchronization, and performs frame synchronization using this frame pattern. This makes it possible to achieve frame synchronization and block synchronization without deteriorating information transmission efficiency.

[Conventional technology]

When encoding is performed using normal code conversion rules, the receiving side first establishes block synchronization, decodes it, and then detects a frame pattern in the data signal to establish frame synchronization.

[Problem that the invention seeks to solve]

In the above-mentioned conventional technology, since a pattern identical to the frame pattern may exist in the data signal, there is a possibility that pseudo-synchronization may occur, and there is a drawback that it takes a long time to recover synchronization.

The present invention solves the above-mentioned problems, and aims to provide a code conversion transmission system that takes advantage of the characteristics of the mBnB code, has a short synchronization recovery time, and has a simple circuit configuration.

[Means for solving problems]

The present invention provides a method for converting a plurality of m-bit human input data signals into a plurality of n-bit (m<n) codewords and transmitting the converted data. It is characterized in that the bits to which no information is assigned are assigned to a frame pattern for synchronization, and the receiving side detects this frame pattern to establish block synchronization and frame synchronization.

[Effect]

Generally, the mBnB code (m<n) is created by selecting a codeword with a mark rate of about 0.5 and a minimum number of consecutive identical codes from 2'' codewords to generate 211 original signals. Therefore, the (2"-2"') n-bit patterns have the information power (unassigned) of the input data signal.

The present invention focuses on this n-bit pattern and assigns it as a frame synchronization pattern. This makes it possible to simplify the frame synchronization circuit and shorten the synchronization recovery time.

〔Example〕

Next, the present invention will be explained with reference to an embodiment of the apparatus shown in the accompanying drawings.

FIG. 1 shows an embodiment of the present invention. FIG. 1 (al is a block diagram of a transmitting section, and FIG. 1(b) is a block diagram of a receiving section.

At the transmitter ia+, the data signal is sent to the serial/parallel converter circuit 1, mBn.
Frame pulses input to the cascade circuit consisting of the B encoding circuit 2 and the parallel-to-serial conversion circuit 8r3 are input to the mBnB encoding circuit 2 via the serial-to-parallel conversion circuit 1 and the frame pattern insertion circuit 4. In the receiving section fbl, the input signal passes through a cascade connection circuit of a serial-to-parallel conversion circuit 6, an mBnB decoding circuit 7, and a parallel-to-serial conversion circuit 8, and outputs a data signal. Further, the input signal is outputted as a frame pulse via the serial/parallel converter 8 and inputted to the serial/parallel converter 6. The data signal input to the transmitter is expanded in parallel into m bits by the serial/parallel conversion circuit 1, converted into an n-bit code word by the m, BnB encoding circuit 2, and then converted into serial data by the parallel/serial conversion circuit 3. converted into a signal. Further, at the position where the frame pulse is input, an n-bit pattern to which no information is assigned is inserted as a frame pattern by the frame pattern insertion circuit 4.

, FIG. 1 (bl is a block diagram of the receiving section. When an encoded serial signal is input, an n-bit frame pattern is detected in the synchronization circuit 5, and frame synchronization is established at the same time as the block synchronization. When block synchronization is established, the serial-to-parallel converter circuit 6 expands the code words into n-bits in parallel, and the mBn'B decoding circuit 7 decodes them into m-bit data signals, followed by parallel-to-serial conversion. It is converted into a serial signal in circuit 8.
Figure 2 shows two sides of the frame structure at the B n B coding level. Information corresponding to the input data signal is not assigned to the n bits at the beginning of the frame, and a pattern that never appears as data (in this example, all 1's) is inserted into this n bit part for synchronization. Make it a pattern.

〔Effect of the invention〕

As explained above, the frame synchronization method in the code conversion transmission method of the present invention has the following features: +l) block synchronization and frame synchronization can be established simultaneously, (2) synchronization recovery time is short, and (3) frame pattern detection circuit. This has effects such as simplification of protection circuits and protection circuits.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a transmitting section and a receiving section of an apparatus according to an embodiment of the present invention. FIG. 2 is an example diagram of a frame structure. DESCRIPTION OF SYMBOLS 1... Serial-parallel conversion circuit, 2... m B n B encoding circuit, 3... Parallel-serial conversion circuit, 4... Frame pattern insertion circuit, 5... Synchronization circuit, 6... Serial-parallel conversion circuit, 7... mBnB decoding circuit, 8... Parallel-serial conversion circuit. (a) Transmitting section (b) Receiving section Fig. 2

Claims (1)

[Claims] (1) Input data signals of multiple m bits to multiple n bits (
In the method of converting into a code word with m<n) and transmitting it, the transmitting side allocates the bits after the code of the above n bits to which information of the input data signal is not allocated to a frame pattern for synchronization, and the receiving side Now, a code conversion transmission method is characterized in that block synchronization and frame synchronization are established by detecting this frame pattern.