JPH0123016B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an SC (Service and Control) bit superimposition method, and particularly to a method for superimposing SC bits on an mBnB code used in optical communication systems and the like.

The mBnB code (m, n are integers, mn) is a code obtained by dividing the original code, such as a binary code such as a PCM code, into m-bit units and converting the m-bit binary code into an n-bit binary code. Since it is possible to set the mark rate of the converted signal, that is, the transmission line signal, to a constant value such as 1/2, regardless of the mark rate of the original signal, it has recently attracted attention as a transmission line code for optical communication systems. ing. For example, in a 3B4B code, as shown in Figure 1a, a 3-bit original binary code (3B) is converted into a corresponding 4-bit binary code (4B).
Convert to For example, the original codes 000, 001, etc.
Converted to 0011, 0101, etc. However, in the example of FIG. 1a, the original codes 110 and 111 are each associated with two sets of 4-bit codes. This means that the 4-bit codes associated with the original codes 000 to 101 are composed of the same number of "0" and "1", and the disparity (difference between the numbers of "0" and "1") d
is 0, whereas these original codes 110 and
In the 4-bit code associated with 111, the numbers of ``0'' and ``1'' are different, so by alternately converting them to codes with different disparity.
This is to make the mark rate of the 3B4B code 1/2. That is, these original codes 110 and
111 is code 0100 with disparity of -2.
and 0010 or sign with disparity +2
1011 and 1101 alternately. Therefore, in the example shown in Figure 1a, the 3-bit original codes have different disparity (d=0, -2, +
2) As shown in the state transition diagram in Figure 1b, the state +1 is converted into a code in which the number of "1"s is greater than the number of "0"s, that is, the mark rate is If the state is 1/2 or more, and state -1 is a state where the number of "1"s in the converted code is less than the number of "0"s, that is, the mark rate is less than 1/2, then disparity d = 0. When converting to a code, there is no state transition regardless of which state (+1 or -1) it is in. However, when converting to a code whose disparity is not 0, the disparity is selected according to the state at that time. That is, in the case of state +1, the sign is converted to the sign of disparity d=-2 and then transitions to state -1, and in the case of state -1, the sign is converted to the sign of disparity d=+2, and thereafter the sign changes to state +1. By such code conversion, the mark rate of the transmission path code can be reduced to approximately 1/2.

By the way, in optical communication systems and the like, control signals or audio signals of each repeater are transmitted as SC bits superimposed on transmission data signals. Conventionally,
The method of superimposing SC bits on mBnB code is as follows:
As shown in Figure 2, a frame F is constructed by dividing the original code into words 1, 2, 3, etc., each consisting of m bits, and dividing it into multiple words (6 words in the figure). A system has been proposed in which a frame bit FB for frame synchronization is inserted into a specific word, and an SC bit is inserted into the specific word as necessary. In this case, each m-bit word of the original code is converted to an n-bit corresponding code to form a transmission line code.
For the word into which the frame bit FB and SC bit SCB are inserted, the m-bit original code is used as is. In Figure 2, words 2, 3, and
5, 6,... are words 2', 3', 5', 6', etc. converted to n-bit corresponding codes, but words 1, 4, 7,... of the original code are used as they are. It is being

However, in the conventional example, since there are words in each frame that are not code-converted, mark rate fluctuations become significant especially when the number of words in one frame is small, making it impossible to fully utilize the advantages of the mBnB code. It was hot.

In view of the problems in the conventional example described above, an object of the present invention is to invert the m-bit original signal and m-bit original signal in the SC bit superimposition method in the word into which frame bits are inserted and the word into which SC bits are inserted. Based on the concept of using signals alternately, it can be achieved using simple hardware.
The objective is to make it possible to accurately superimpose SC bits while taking advantage of the features of the mBnB code.

In an SC bit superimposition method in a communication system using an mBnB code as a transmission line code, the present invention performs code conversion of an m-bit original signal at a constant cycle for words into which frame bits are inserted and words into which SC bits are inserted. It is characterized in that it uses a signal obtained by inverting each bit of the original signal of bits or the original signal of m bits, and converts the other words into an mBnB code of n bits corresponding to the original signal of m bits.

Embodiments of the present invention will be described below with reference to the drawings. In the present invention, as shown in Figure 3a, the m-bit original signal mB is used as is in the word into which the frame bit FB is inserted, and the inverted signal of the m-bit original signal is used in the word into which the SC bit SCB is inserted. Or, as shown in FIG. 3b, the word in which the frame bit FB is inserted uses the inverted signal of the m-bit original signal, and the word in which the SC bit SCB is inserted uses the m-bit original signal mB as is. Words other than the word into which the frame bit FB is inserted and the word into which the SC bit SCB is inserted are conventionally converted into an n-bit binary code nB, that is, an mBnB code, corresponding to each m-bit original signal.

Alternatively, as shown in FIG.
Original signal mB and inverted signal of the original signal per frame)
mB may be used alternately. In addition, as shown in Figure 4b, the word with frame bit FB inserted and
The original signal mB and its inverted signal may be used alternately for each independent cycle in words into which the SC bit SCB is inserted. Figure 4b shows that in words with frame bits inserted, the original signal mB and its inverted signal are used alternately every frame, and in words with SC bits inserted, the original signal mB and its inverted signal are alternately used every two frames. The state when used is shown.

By the way, as mentioned above, when the original signal mB and its inverted signal are used alternately for the word into which the frame bit FB is inserted and the word into which the SC bit is inserted, the mark rate of the transmission line signal is a constant value (for example, 1/2). I will explain the reason why. For example, if the original signal regularly repeats 1's and 0's in a certain period _T1 , the above-mentioned original signal mB and its inverted signal
Let the period T ₂ using mB be different from the period T ₁ and
T ₁ ≠kT ₂ (k=1, 3, 5,..., i.e. odd number)
By selecting ``1'' and ``0'' in the transmission path signal, the probability of occurrence of ``1'' and ``0'' can be made almost equal, and the mark rate can therefore be reduced to approximately 1/2.
Note that all words in which frame bits FB and SC bits SCB are not inserted are converted to n-bit mBnB code signals, so the mark rate for these words is a constant value of approximately 1/2 mark rate due to the nature of mBnB codes. That is clear. Next, if consecutive 1's and consecutive 0's occur randomly in the original signal, the probability that "1" in the original signal becomes "1" by using the original signal mB as is is 1/2, By using an inverted signal of the original signal, the probability that "1" becomes "0" also becomes 1/2. Also,
The probability that the original signal "0" becomes "0" by using the original signal mB as is is 1/2, and the probability that the original signal "0" becomes "1" by using the inverted signal of the original signal is also 1. /2. Therefore,
The mark rate of the transmission line signal is a constant value of 1/2. Furthermore, if the mark rate of the original signal is close to 1 or 0, the word and
The word SCB with the SC bit inserted contains the original signal mB.
It is clear that the mark rate is a constant value of 1/2 because the inverted signal and the inverted signal thereof are used. Therefore, the mark rate of the transmission path code created by the method of the present invention is approximately constant.

FIG. 5 shows the configuration of an mBnB encoder (coder) provided on the transmitting side of an optical communication system, etc. The coder converts the original signal into a transmission line code using the mBnB code as described above, and also converts the SC bits. Has the ability to insert. The coder in Figure 5 includes a serial-to-parallel conversion circuit 1, a code conversion circuit 2 consisting of ROM (read-only memory), etc., a parallel-to-serial conversion circuit 3, a frequency divider circuit 4, a timing generation circuit 5, a delay circuit 6, and a switch circuit. 7 and a multiplier circuit 8.

In the configuration shown in FIG. 5, the original signal in serial format is input to the serial-parallel conversion circuit 1 together with the basic clock (frequency ₀ ) of the original signal and a clock with a frequency ₀ /m divided by m by the frequency dividing circuit 4. and converted into a parallel signal of every m bits. The parallel signals are input to the code conversion circuit 2, where they are converted into corresponding n-bit parallel signals, and further into the parallel-to-serial conversion circuit 3, where each word is converted into a serial format consisting of n bits.
Converted to mBnB signal. Here, a clock with a frequency of ₀ /m from the frequency divider circuit 4 and a clock with a frequency (n/m) ₀ obtained by multiplying the clock by n in the multiplier circuit 8 are applied to the parallel-to-serial converter circuit 3. control is performed. In addition,
The delay circuit 6 stores the disparity of the n-bit parallel output signal converted by the code conversion circuit 2, and is used to convert it into an n-bit signal having a disparity different from the disparity when converting the code of the next word. Therefore, the output of the delay circuit 6 is input to the code conversion circuit 2 during code conversion of the original signal to which two n-bit words having mutually different disparities are assigned.

Furthermore, in the code conversion circuit 2 described above, a frame bit FB is inserted for each predetermined word, and the frame bit FB is inserted into, for example, the first bit of the n-bit parallel output, and is inserted through the output line _l1 . and is input to the parallel-to-serial conversion circuit 3. Further, in the timing generating circuit 5, a switch control signal SWC is generated for each predetermined word based on the clock of frequency ₀ /m from the frequency dividing circuit 4, and is applied to the switch circuit 7. switch circuit 7
is switched for each predetermined word based on the switch control signal SWC as shown by the dotted line in Figure 5,
From the SC signal input, the SC bit SCB is inserted into the first bit of the n-bit parallel output.

In order to insert the original signal mB or its inverted signal into the word into which the frame bit FB and SC bit SCB have been inserted as described above, the timing generation circuit 5 generates mB at a predetermined timing when converting the code of each word. A command pulse or a command pulse is input to the code conversion circuit 2. When the mB command pulse is input, the code conversion circuit 2
The input signal of bits is sent as it is to predetermined m lines among the output lines _L2 to _L0 , and when a command pulse is input, a signal in which each bit of the m-bit input signal is inverted is sent to the output lines _L2 to L0. l Send to a predetermined m number of _o .

FIG. 6 shows the configuration of an mBnB decoder (decoder) provided on the receiving side. The decoder returns the transmitted mBnB signal to the original signal and also converts the SC bit inserted into the mBnB code as described above.
Has the ability to extract SCB. mBnB in Figure 5
The code decoder is a serial/parallel converter circuit 11, ROM
A decoding circuit 12, a parallel-to-serial conversion circuit 13, a frequency dividing circuit 14, a timing generation circuit 15, etc.
Synchronous protection circuit 16, delay flip-flop 1
7 and a multiplier circuit 18.

In the configuration shown in FIG. 6, the received data input in serial format, that is, the transmission line signal using the mBnB code, is serially connected to a clock with a frequency of (n/m) ₀ and a clock with a frequency of ₀ /m created by the frequency divider circuit 14. The signal is input to the parallel conversion circuit 11 and converted into a parallel signal every n bits. This n-bit parallel signal is input to the decoding circuit 12 and converted into a corresponding m-bit parallel signal, and then the parallel-to-serial conversion circuit 1
3, it is converted into an original signal in serial format. Here, a clock with a frequency of ₀ /m from the frequency divider circuit 14 and a clock with a frequency of ₀ obtained by multiplying the clock by m in the multiplier circuit 18 are applied to the parallel-to-serial conversion circuit 13 to control the timing.

The timing generating circuit 15 generates various timing pulses based on the clock having a frequency of ₀ /m from the frequency dividing circuit 14. For example, the synchronization protection circuit 1 creates a frame timing pulse with a predetermined period.
Enter 6. The synchronization protection circuit 16
Taking in a signal from one output line of the serial-parallel conversion circuit 11 by a timing pulse, determining whether the signal is a frame bit FB signal, that is, determining whether frame synchronization is established; Information as to whether frame synchronization is achieved is input to the frequency dividing circuit 14 as control information CT.
According to the control information CT, if frame synchronization is not achieved, the input clock of the frequency divider circuit 14 is set to 1.
Processing such as bit removal is performed, and the output clock from the frequency dividing circuit 14 is processed to ensure frame synchronization.
The phase of ₀ /m is adjusted.

In addition, the timing generation circuit 15 generates mB command pulses at the same timing as the coder on the transmitting side.
The mB command pulse is input to the code conversion circuit 12, and control is performed so that the original signal mB is reproduced in the word into which the frame bit FB is inserted and the word into which the SC bit SCB is inserted. Furthermore, the timing generation circuit 15 inputs the SC signal timing pulse to the clock input of the delay flip-flop 17,
An SC signal output is generated according to the level of the SC bit at the rising or falling point of the timing pulse.

As described above, according to the present invention, it is possible to accurately superimpose SC bits while taking advantage of the features of the mBnB code using simple hardware, and even when the frame length is short, the mark rate fluctuation is small and almost constant. Since it can be converted into a value, the features of the mBnB code are not lost.

[Brief explanation of drawings]

Figures 1a and 1b are explanatory diagrams showing an example of mBnB code, Figure 2 is an information layout diagram for explaining the conventional SC bit superimposition method, and Figures 3 and 4 are , an information layout diagram for explaining the SC bit superimposition method according to the embodiment of the present invention, FIG.
A block circuit diagram showing an example of an mBnB encoder (coder) for implementing the method of the present invention, and FIG. 6 shows an example of an mBnB decoder (decoder) for implementing the method of the present invention. FIG. 3 is a block circuit diagram. 1...Serial parallel conversion circuit, 2...Sign conversion circuit, 3
...Parallel-serial conversion circuit, 4...Frequency divider circuit, 5...Timing generation circuit, 6...Delay circuit, 7...Switch circuit, 8...Multiplier circuit, 11...Serial-parallel conversion circuit, 1
2...Decoding circuit, 13...Parallel-serial conversion circuit, 14...
Frequency divider circuit, 15...Timing generation circuit, 16...Synchronization protection circuit, 17...Delay flip-flop,
18... Multiplier circuit.

Claims (1)

[Claims] 1. In an SC bit superimposition method in a communication system using an mBnB code as a transmission path code, m
The code conversion of the original bit signal is carried out using the m-bit original signal or a signal obtained by inverting each bit of the m-bit original signal at a constant cycle for words into which frame bits are inserted and words into which SC bits are inserted.
An SC bit superimposition method characterized by converting other words into an n-bit mBnB code corresponding to an m-bit original signal. 2. In the word with frame bits inserted at the constant period, the m-bit original signal is used as is, and the SC
Words with bits inserted use the m-bit original signal with each bit inverted, or words with frame bits inserted use the m-bit original signal with each bit inverted. In the SC bit superimposition method according to claim 1, the m-bit original signal is used as is. 3. The fixed period is defined as one frame, and the m-bit original signal of a word into which a frame bit is inserted and a word into which an SC bit is inserted is inverted every other frame. SC bit superimposition method. 4. The constant period is a fixed interval regardless of the period of the word into which the frame bit is inserted and the word into which the SC bit is inserted, and the m-bit original signal and the inverted version of each bit of the m-bit original signal are classified. 2. The SC bit superimposition method according to claim 1, wherein the SC bit superposition method is used alternately at fixed intervals.