JPS5917749A - Transmission system of digital signal - Google Patents

Abstract

PURPOSE:To superimpose and transmit a low-speed digital signal without raising the bit rate, by sampling and inserting low-speed data to C bits when a high- speed digital signal is encoded to an mBIC code. CONSTITUTION:The high-speed digital signal inputted from a terminal 26 is subjected to speed conversion 28 for the purpose of inserting C bits, frame synchronizing bits, control bits for changeover switcher, etc., and idle bits are secured on a high-speed digial signal sequence. Frame synchronizing bits are inserted to this signal sequence by a frame inserting means 29, the signal sequence is made random by a scrambler 30. The signal sequence is subjected to mBIC code conversion in an encoding part 31, and simultaneously, the low-speed digital signal inputted from a terminal 27 is sampled by a sampling means 32 and is inserted to preliminarily determined C bits, and the signal is transmtted to a transmission line 33. In the receiving side, the frame synchronizing pulse is detected by a detector 35 to astablish the frame synchronization, and low-speed data superimposed upon C bits is smoothed by a smoothing means 36 to restore low-speed data, and the high-speed signal is descrambled by a descrambler 38 is restored by speed conversion in a means 39.

Description

[Description of the field to which the invention pertains] The present invention relates to a digital signal transmission system that superimposes a low-speed digital signal such as a game warning signal or a voice for a meeting (in-sign) on a high-speed mBlc code and transmits the superimposed signal. .

Here, the mBlc code is m on the binary information sequence.
+17 m speed conversion is performed, one redundant bit (hereinafter referred to as 'CC pit) is secured for every m bits, and the complementary code of the information bit (I bit) located at a specific position relative to the C bit is converted to this bit. A code inserted into the C bit. By employing such a code structure, it is possible to definitely suppress the worst case of consecutive same codes, thereby stabilizing the transmission quality.

[Description of prior art]

Conventionally, in order to multiplex and transmit a high-speed digital signal and a low-speed digital signal on a suspended transmission line, such as in a digital optical submarine cable system, after time division multiplexing both signals, a code format suitable for the transmission line was used. It is performed to convert the data into

FIG. 1 shows a block diagram of a main part of a transmitter of a conventional device, and FIG. 2 shows a block diagram of a main part of a receiver of a conventional device. The high-speed digital data is inputted as a data and clock pair from a high-speed data signal input terminal 1 and a high-speed clock/electronic input terminal 2, respectively. The same goes for low-speed digitization, where data and clock are input as a pair from the low-speed data signal input terminal 3 and the low-speed clock pulse input terminal 4. These high-speed data and low-speed data signals are once input into the breadthreader memories 5 and 6 using high-speed clock pulses and low-speed clock pulses. now,
Let the high-speed clock frequency be fh and the low-speed clock frequency be f
Since the clock frequency fm of the time-division multiplexed digital signal includes a frame synchronization pulse, f),
+fl will be slightly higher. A multiplexed clock signal ξ having a frequency fm is inputted from the multiplexed clock signal input terminal 7.

The frame pattern generation circuit 8 generates a frame synchronization signal ξ from the multiplexed clock signal ξ, and also supplies a readout signal to the frame memories 5 and 6. The multiplexing gate 9 combines the signals read from the buffer memories 5 and 6 and the frame synchronization noise ξ of the frame pattern generation circuit 8 into one signal. This combined signal is converted by the encoding circuit 10 into a code format suitable for the transmission line 11 and sent to the transmission line 11.

In addition, in the receiving "FA" (FIG. 2), the signal sent from the transmission line 11 is equalized and amplified and discriminately reproduced by the reproducing circuit 15, and is input to the decoding circuit 16. The ξ pulse is reproduced and supplied to a decoding circuit 16 and a frame synchronization circuit 17.The decoding circuit 16 performs the reverse operation of the encoding circuit 10 to restore the original time division multiplexed signal.Frame synchronization circuit At step 17, a frame synchronization pulse is detected from this signal to determine the frame period.At the same time, a control pulse is supplied to the demultiplexing gate 18.

The multiplex valve internal IF gate 18 separates the time-division multiplexed signal into a high-speed digital signal and a low-speed digital signal, and writes them into buffer memories IJ19 and 20, respectively.

The contents of the buffer memories 19 and 20 are read out by high-speed clock pulses and low-speed clock pulses input from the high-speed clock pulse input terminal 21 and the low-speed clock pulse input terminal 22, and are read out from the high-speed data signal output terminal 23 and the low-speed data signal output terminal, respectively. 24. These high-speed and low-speed clock pulses are reproduced by the regeneration circuit 1.
P L L (
phase 1ocked 1oop) etc.

In this way, in the conventional method, the bit rate of the time-division multiplexed signal is higher than the bit rate of the high-speed digital signal (because it is higher than the bit rate of the high-speed digital signal, the transmission distance etc. In order to perform signal speed conversion on the transmitting side, a generator for multiplexed clock pulses with a frequency higher than the high-speed clock frequency is required, which has disadvantages such as making the device complicated and expensive.

[Purpose of the invention]

The present invention improves this point, and provides a digital transmission system that can superimpose a low-speed digital signal on a high-speed digital signal without increasing the bit rate when mBlc encoding the high-speed digital signal. With the goal.

[Summary of the invention]

The present invention converts the speed of high-speed data input to an input terminal and converts it into m bits (m is a positive integer) on a high-speed digital signal sequence.
a speed conversion circuit that generates one redundant bit for each bit, and an encoding circuit that inserts a complementary code of an information bit having a fixed positional relationship with the redundant bit into the position of the redundant bit and performs mBlc encoding, mB1cB with one transmission path
In a digital signal transmission system that transmits and receives unified digital signals, a low-speed data sampling circuit that samples low-speed data input to another input terminal;
A frequency dividing circuit for controlling the sampling rate of the low-speed data sampling circuit, and circuit means for preferentially inserting the output into at least some positions of the redundant bits when the low-speed data sampling circuit has an output. It is characterized by:

[Explanation based on examples]

An embodiment of the present invention will be explained based on the drawings.

FIG. 5 is a block diagram of main parts of an embodiment of the present invention. In FIG. 6, 26 indicates a high-speed data input terminal, and 27 indicates a low-speed data input terminal. High speed data input terminal 26
is connected to the speed conversion section 28 , this output is guided to the frame insertion section 29 , this output is guided to the scrambler 30 , and this output is guided to the mBIC code conversion section 31 . Further, the low-speed data input terminal 27 is led to the low-speed data sampling section 32, and the output thereof is led to the ml1lc code conversion section 31. The output of this mBIC code converter 31 is guided to the transmission line 33 (.

This transmission line 33 is connected to a frame synchronization section 35, and the output thereof is guided to a low-speed data smoothing section 36 and a descrambler 38, respectively, and this output is guided to a speed conversion section 39. The high-speed data output terminal 41 is a low-speed data smoothing section 36.
The low-speed data output terminals from which the outputs of are led are shown.

With such a circuit configuration, the mBlc code is a redundant configuration code, and low-speed data transmission is possible using the C bit. That is, the present invention inserts rl- into the C bit when the low-speed data is rlJ, and when the low-speed data is 10. In this case, by inserting 1゛OJ into the C bit, the C bit is controlled so that the C bit information matches the low speed data.

Now, the high-speed digital signal input from the high-speed data input terminal 26 is speed-converted by the speed converter 28 in order to insert the C bit, frame synchronization bit, control bit for the changeover switcher, etc., and the bits are converted into the high-speed digital signal. Reserved on the series. A frame synchronization bit is inserted into this high-speed digital signal sequence in a frame insertion section 29. Next, the 1 scrambler 30 randomizes the input high-speed digital signal sequence.

Finally, the mBlc code conversion unit 31 performs mBIC code conversion, and at the same time inserts a code selected based on the low-speed digital signal manually input from the low-speed data input terminal 27 into a predetermined C bit, and sends it to the transmission line 33. do.

In this case, the low-speed digital signal is subjected to multi-point sampling/sampling by the low-speed data sampling section 32, and the above-mentioned C-bit control is performed on each sample bit.

On the other hand, on the receiving side, a frame synchronization section 35 detects a frame synchronization pulse from the signal and establishes frame synchronization. At the same time, the low-speed data superimposed on the C bit is extracted to the low-speed data smoothing section 36 in a multi-point sampling state.

This low-speed data is smoothed by the low-speed data smoothing section 36 using the original low-speed clock, and the input low-speed data is restored.

Here, the low-speed clock is a timing component extracted from the received signal as P L L (phase 1 locked 1
oop) and generate it. Next, the high-speed digital signal from which the C bits have been extracted is decoded by the descrambler 38 and speed converter 39, and only the original input digital signal sequence is output from the high-speed data output terminal 40.

This will be explained in more detail. Figure 4 shows mBlc
3 is a detailed diagram of a low-speed data insertion portion of the code conversion unit 31. FIG.

In FIG. 4, 45 is a high-speed data signal input terminal, 46 is a high-speed data clock input terminal, 47 is a low-speed data input terminal,
48 indicates high-speed data signal output terminals. This high-speed data input terminal 45 is led to the D input terminal of the register 51 of the shift register section 50, and this Q output terminal is led to the D input terminal of the register 52.
The Q output terminals of the complementary code) ξ pulse position command section 53 are led to the D input terminals of the registers 54 and 55, respectively, and the Q output terminals are connected to the AND circuit 58.55 of the complementary code control pulse generation section 57.
59, respectively.

In addition, the high-speed data clock input terminal 46 is set to a frequency division ratio of 17m.
+1 frequency divider circuit 60, and this output is connected to a 7-nd circuit 6.
1 to the clock terminals of the registers 54 and 55.
It is also connected to the D input terminal of the register 62. The Q output terminal of this register 62 is connected to the above 771 circuit 58.59.
It is connected to the other input terminals of Sakaki and K, respectively. This AND circuit 5
The output of 8.59 is connected to the input terminal of the arbitrary OR circuit 63.
Circuit 66.67 1! Inversion input terminal and AND circuit 68
In addition, the Q output terminal of the register 62 is connected to the input terminal of the AND circuit 68, and
670 to the inverting input terminal, respectively, and the Q output terminal 1, 0, and Q output terminal of the register 52 are respectively led to the delay circuits 71 and 72 of the delay circuit section 70, and the output of this delay circuit 71 is Input 1 of the above AND circuit 66.68
'jjn, respectively, and the output of the delay circuit 72 is connected to the input terminal K4 of the AND circuit 67.

Further, the output of the frequency dividing circuit 60 is led to a frequency dividing circuit 74 with a frequency division ratio of 1/, and this output is led to the input terminals of a fast data ZANZORING circuit 75, a NOT circuit 69, and an AND circuit 760, respectively. This low-speed data sampling circuit 75
The output of the AND circuit 66 and 68 is connected to the other input terminal of the amplifier circuit 76.
respectively to the input terminals, and connect this output with the above knot circuit 6.
9 outputs are respectively led to AND circuit 800 input terminals,
This output and the output of the ambi circuit 76 are ORed by a circuit 81
0 input terminal, respectively, and its output is led to the D input terminal of the shaping circuit 82, and its Q output terminal is led to the high speed data signal output terminal 48 (.

Further, the high speed data clock input terminal 46 is connected to the register 51, 52, 62, and the clock terminal C of the shaping circuit 82.
, 771 and the input terminals of the circuit 61 and the low-speed data sampling circuit 75, respectively. Furthermore, high-speed data and clocks are synchronized.

FIG. 5 shows the frequency division ratio of the frequency division circuit 60.74, which is 17m+1.
．． Figure 4 shows X when 1/k is set to m = 3, k-3.
It is an operation time chart showing signal waveforms at points I to I indicated by marks.

With this circuit configuration, the high-speed data input terminal 45 ((() is speed-converted and high-speed data DATAI with an empty bit (C bit) every m + 1 bits is input (the C bit is the (4) of DATA1 in FIG. ), (8), (12) bits).This high-speed data DATAI is stored in the shift register section 5.
0, the signal is shifted in synchronization with the clock CLK input from the high-speed data clock input terminal 46. This shifted Q, output and. The output complementary signals Q and Q2 of the two outputs are applied to the complementary symbol in synchronization with the 1/m-4-1 clock pulse C1 generated from the frequency dividing circuit 6o.
3rd to mth bit output complementary code pulse Q1 and m +
It is outputted as an in-phase signal as the 1st bit output complementary forward signal pulse Q/. this. The 1 output and the 96 output are gated by the C2 output which is output for each time slot position of the C bit which is the output of the register 62, and is gated by the AND circuit 58.59.
C1, (is combined and output. This output and q output are exclusive ORed in an exclusive OR circuit 63, and the complementary code insertion section 65 outputs Q2 as a complementary code. °C is 4 ．．
An output selection signal QEX is output. i.e. this output. If EX is r(3-), the signals of the m-th bit and the m+1-th bit are determined to have the same sign, and the complementary code insertion unit 65 inserts m
-1-1 bit (C bit) AND circuit 67 to 6
．． The output is selected and output through the OR circuit 79, the AND circuit 8o, and the OR circuit 81 to the high-speed data signal output terminal 48 in synchronization with the clock CLK. As a result, if the output QEX is f″1., the m-th and m+1-th bit signals are determined to have different signs, and the complementary code insertion unit 65 inserts m
+ AND circuit 68 to Q on the 1st bit (C bit)
Two outputs are selected and output through the OR circuit 78, the AND circuit 80, and the OR circuit 81 to the high-speed data signal output terminal 48 in synchronization with the clock CLK.

In addition, for bits other than the m-1-1th bit, the above QEX
The output and the C2 output are not sent out and the complementary code inserting unit 65 7
Q2 output is selected from 71 circuit 66 and OR circuit 78.7
9. AND circuit 80. The signal passes through the OR circuit 8 and is output to the high-speed data signal output terminal /18 in synchronization with the clock CLK.

Next, the case where low-speed data is superimposed on the C bit, which is a feature of the present invention, will be explained. Low-speed data DATA2 is input from the low-speed data input terminal 47, and this low-speed data DATA
2 is subjected to multiple sampling by a high-speed data sampling circuit 75. At this time, the sampling rate fs is the frequency of the clock CLK. If the number of sample points is kX(m-)-1)/sec, then f.

becomes. The sampled low-speed pulse C1 is output from the C1 frequency divider circuit 74 every k (m+1) bits, and the C8 output is inserted into the C bit through the AND circuit 76 and sent out from the high-speed data signal output 48.

Here, when the C5 output is sent out from the frequency divider circuit 74, the AND circuit 80 is closed by the inverted output of the C3 output, and low-speed data is preferentially inserted into the C bit. m
= 3, when k=3, D A T A in Fig. 5
The previous bit Sleeve E1, that is, C2 or C2, is inserted into the C bit shown in the shaded area in OUT, and low-speed data C4 can be inserted into the third C bit where the C3 output is sent. I understand.

In addition, in the above embodiment, a case was shown in which low-speed data is inserted between the terminal stations and transmitted by inserting the low-speed data into the C bit, but frame synchronization is also performed at the intermediate repeater, and a predetermined By selecting the specified C bit, it is also possible to sample temperature information and laser monitoring information and insert it into the C bit for remote monitoring. This is particularly effective when the bit rate of low-speed data to be inserted is slow.

〔Effect of the invention〕

As explained above, according to the present invention, when a high-speed digital signal is mH1c encoded, low-speed data is sampled and inserted into the C bit. therefore,
Low-speed digital signals can be transmitted thereto by relatively simple hardware configuration without increasing the bit rate.

This is particularly effective when attempting to simultaneously transmit high-speed digital signals and low-speed digital 414 signals using one transmission path, such as in a digital optical submarine cable system. In addition, the C-bit effect can also be achieved by inserting monitoring information into the C bit to enable long-distance monitoring.

[Brief explanation of drawings]

FIGS. 1 and 2 are block diagrams of main parts of a conventional device. FIG. 5 is a block diagram of a main part of an embodiment of the invention. FIG. 4 is a detailed diagram of the mBlc code conversion section. Figure 35 is an operation time chart showing the signal waveform at the point indicated by the X mark in Figure 4. 5.6.19.20... Buffer memory, 9... Multiplexing gate, 10... Encoding circuit, 11.33...
1. For transmission. j. 15... Reproduction circuit, 16... Decoding circuit, 17...
・Frame synchronization circuit, 18 -- Separation gate, 28.3
9... Rapid conversion section, 29 Pa frame insertion section, 30.
...Scrambler, 31...m111c code conversion unit,
32...Low speed data sampling section, 35...Frame synchronization section, 36...Low speed data smoothing sound IX
, 38... Descrambler, 50... Shift register section, 53... Arm pulse position designation section, 57...
Complementary code control pulse generator, 60.74...frequency dividing circuit,
65... Complementary code insertion section, 75... Low-speed data sancilling circuit. Patent Applicant Nippon Telegraph Telephone Public Corporation Agent Patent Attorney Ide Nao Takashi 1 dl EX 4 M 5 Ro

Claims (1)

[Claims] (1) A speed conversion circuit that converts the speed of high-speed data input to the input terminal and generates one redundant bit for every m bits on the high-speed digital signal sequence, and a Information bit sleeve? In a digital signal transmission system that transmits and receives mBlc-encoded digital signals through one transmission path, the system is equipped with a signal encoding circuit that inserts a tE+ code into a redundant bit position and performs mBlc encoding. A low-speed data sampling circuit that samples input low-speed data, a frequency divider circuit that controls the sampling rate of this low-speed data summing circuit, and when the low-speed data sampling circuit has an output, this output is transferred to the low-redundant bit ( A digital signal transmission method characterized by comprising: a circuit means for preferentially inserting a signal into a certain position.