JPS61253958A - Digital communication system - Google Patents

Digital communication system

Info

Publication number
JPS61253958A
JPS61253958A JP60095030A JP9503085A JPS61253958A JP S61253958 A JPS61253958 A JP S61253958A JP 60095030 A JP60095030 A JP 60095030A JP 9503085 A JP9503085 A JP 9503085A JP S61253958 A JPS61253958 A JP S61253958A
Authority
JP
Japan
Prior art keywords
digital signal
terminal
signal
clock
bit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60095030A
Other languages
Japanese (ja)
Inventor
Masatoyo Tsunoda
正豊 角田
Hisao Tsuji
辻 久雄
Nobuaki Fujii
伸朗 藤井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP60095030A priority Critical patent/JPS61253958A/en
Publication of JPS61253958A publication Critical patent/JPS61253958A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To make a signal synchronize with a clock generated from a terminal equipment with a comparatively simple constitution by converting respective bits of a binary digital signal consisting of '0' and '1' into the 1st and 2nd serial 3-bit codes in accordance with the '0' and '1' on the transmitting side. CONSTITUTION:On the transmitting side 21, a binary digital signal consisting of '0' and '1', having 1/f bit period and outputted from a digital signal source 22 is converted into the 1st and 2nd serial 3-bit codes in accordance with the '0' and '1' by a code converter 23 and the 1st and 2nd 3-bit codes are sent to a transmission line 24. A digital signal of 3f inputted to an input terminal 11 is amplified by an amplifier 12 and branched into two signals and one branched signal is inputted to an elastic memory 16. The other branched signal is inputted to the writing clock terminal CK of the elastic memory 16 through a delay circuit 26 having 1/2f delay. A clock from a terminal equipment is inputted from a terminal 17 to the reading clock terminal of the elastic memory 16 and a digital signal of frequency (f) which is regenerated synchronously with the terminal equipment clock is outputted to an output terminal 18.

Description

【発明の詳細な説明】 「産業上の利用分野」 この発明は構成が簡単なディジタル通信送受信機に関す
るものである。
DETAILED DESCRIPTION OF THE INVENTION "Field of Industrial Application" The present invention relates to a digital communication transceiver with a simple configuration.

「従来の技術」 ディジクル通信方式では端局装置において4重化を行う
ため、端局装置で受信された信号を端局装置のクロック
に同期させる必要がある。このため従来のディジタル通
信受信機は第6図に示すように構成されていた。即ち入
力端子11に受信されたディジタル信号は増幅器12で
増幅された後、2つに分岐され、その一方の信号はタン
ク回路13に入力される。タンク回路13でその入力デ
ィジタル信号のビット速度と同じ周期の正弦波信号が作
られ、その正弦波信号はスライス増幅器14で矩形波信
号に整形され、その矩形波信号は遅延回路15に通され
て、その矩形波信号の立上りが、前記分岐された他方の
信号のパルス幅の中心とほぼ一致するように調整される
。その調整された矩形波信号と前記分岐された他方のデ
ィジタル信号とがそれぞれ、エラスチックメモリ16の
書き込みクロンク端子CKとデータ入力端子りとに入力
される。端局装置のクロックが端子17からエラスチッ
クメモリ16に与えられてこれが続出され、出力端子1
8に端局装置のクロックに同期した受信ディジタル信号
を得る。
"Prior Art" In the digital communication system, since quadruplexing is performed in the terminal device, it is necessary to synchronize the signal received by the terminal device with the clock of the terminal device. For this reason, conventional digital communication receivers have been constructed as shown in FIG. That is, the digital signal received at the input terminal 11 is amplified by the amplifier 12 and then branched into two signals, one of which is input to the tank circuit 13 . The tank circuit 13 generates a sine wave signal having the same period as the bit rate of the input digital signal, the sine wave signal is shaped into a rectangular wave signal by the slice amplifier 14, and the rectangular wave signal is passed through the delay circuit 15. , the rise of the rectangular wave signal is adjusted so as to substantially coincide with the center of the pulse width of the other branched signal. The adjusted rectangular wave signal and the other branched digital signal are input to the write clock terminal CK and data input terminal of the elastic memory 16, respectively. The clock of the terminal equipment is given to the elastic memory 16 from the terminal 17, and this is successively outputted, and the clock is sent to the output terminal 1.
At step 8, a received digital signal synchronized with the clock of the terminal device is obtained.

「発明が解決しようとする問題点」 しかしこの従来の構成では受信ディジタル信号が“0“
又は“1”が連続した場合、受信ディジタル信号内にそ
のビット速度と同じ周波数成分がなくなり、タンク回路
13に受信ディジタル信号を入力しても、正弦波信号を
再生できないという欠点があった。
“Problem to be solved by the invention” However, in this conventional configuration, the received digital signal is “0”.
Alternatively, if "1" continues, there is no frequency component in the received digital signal that is the same as the bit rate, and even if the received digital signal is input to the tank circuit 13, there is a drawback that a sine wave signal cannot be reproduced.

この欠点を解決するため信号“0”と“1′を、それぞ
れ“01″と“00”又は“11″の交番になるように
2倍のビット速度信号に変換して伝送するCMIやDM
I符号が使用されている。しかしながら、このC旧符号
等の改善案を使用しても、依然としてタンク回路13や
スライス増幅器14が必要であり、回路構成が複雑であ
り、また、エラスチックメモリ16で受信ディジタル信
号と同期をとる際に、タンク回路13やスライス増幅器
14の個々のバラツキがあるため、各装置ごとに遅延回
路15の位相遅延量を調整しなければならず手数が掛る
欠点もあった。
To solve this problem, CMI and DM convert the signals "0" and "1' into double bit rate signals so that they become alternating "01" and "00" or "11" respectively.
I code is used. However, even if this improvement plan such as the C old code is used, the tank circuit 13 and the slice amplifier 14 are still required, the circuit configuration is complicated, and when synchronizing with the received digital signal in the elastic memory 16. Furthermore, since there are individual variations in the tank circuit 13 and the slice amplifier 14, there is also the drawback that the phase delay amount of the delay circuit 15 must be adjusted for each device, which is time-consuming.

この発明の目的は比較的簡単な構成で端局装置のクロッ
クに同期させることを可能とさせるディジタル通信方式
を提供することにある。
An object of the present invention is to provide a digital communication system that allows synchronization with the clock of a terminal device with a relatively simple configuration.

「問題点を解決するための手段」 この発明によれば送信側で“0”、“1”の2値ディジ
タル信号はその各ビットごとにその“0″。
"Means for Solving the Problem" According to the present invention, a binary digital signal of "0" and "1" is converted to "0" for each bit on the transmitting side.

“1”はコード変換部でそれぞれ直列の第1.第2の3
ビットのコードに変換される。これら第1゜第2の3ビ
ットコードはそれぞれ“0″と1″とよりなり、環ディ
ジタル信号の2分の1ビット周期だけ遅延させた時、そ
の1”の予め決めた一方のエツジが第1の3ビットコー
ドは遅延前の“0”と対応し、第2の3ビットコードは
遅延前の1”と対応するものである。つまり第1の3ビ
ットコードは“1′が1ビットであり、第2の3ビット
コードは“1”が連続して2ビットあり、しかも変換さ
れたコードを、原ディジクル信号に従って連続させる時
に、隣接コードは“1′と“0″とにより接続される。
"1" indicates the first . second 3
Converted to bit code. These first and second 3-bit codes consist of ``0'' and 1'', respectively, and when the ring digital signal is delayed by 1/2 bit period, one predetermined edge of 1'' becomes the The 3-bit code for 1 corresponds to ``0'' before the delay, and the second 3-bit code corresponds to ``1'' before delay.In other words, the first 3-bit code corresponds to ``1'' for 1 bit. Yes, the second 3-bit code has two consecutive "1" bits, and when the converted code is continuous according to the original digital signal, the adjacent codes are connected by "1' and "0". .

このコード変換されたディジタル信号は受信側で2分岐
され、その一方は環ディジタル信号の2分の1ビット周
期遅延され、その遅延されたディジタル信号の予め決め
た“1”のエツジで分岐された他方のディジタル信号を
エラスチックメモリに書込む。
This code-converted digital signal is branched into two on the receiving side, one of which is delayed by 1/2 bit period of the ring digital signal, and branched at a predetermined "1" edge of the delayed digital signal. Write the other digital signal to elastic memory.

「実施例」 第1図はこの発明によるディジタル通信方式の実施例を
示す、送信側21においてディジクル信号源22からの
ビット周期が1/f の“0”、“1”の2値ディジタ
ル信号はコード変換器23でその“0”。
"Embodiment" FIG. 1 shows an embodiment of the digital communication system according to the present invention. On the transmitting side 21, a binary digital signal of "0" and "1" with a bit period of 1/f is sent from a digital signal source 22. The code converter 23 converts it to “0”.

“1″に応じてそれぞれ直列の第1.第2の3ビット符
号に変換され、この変換された周波数3fのディジタル
信号は伝送路24へ送出される。
1 in series, respectively. It is converted into a second 3-bit code, and this converted digital signal of frequency 3f is sent to the transmission path 24.

受信側25において入力端子11に入力された3fのデ
ィジタル信号は増幅器12で増幅された後、2分岐され
、その一方はそのままエラスチックメモリ16のデータ
端子りに入力される。前記分岐された他方の受信ディジ
タル信号は1/2fの遅延量を持つ遅延回路26を通過
してエラスチックメモIJ16の書込みクロック端子C
Kに入力される。端局装置クロックは端子17からエラ
スチックメモIJ16の読出しクロック端子に入力され
、端局装置クロックに同期した再生された周波数fのデ
ィジタル信号がデータ読出し端子から出力端子18に出
力される。
The 3f digital signal input to the input terminal 11 on the receiving side 25 is amplified by the amplifier 12 and then branched into two, one of which is input as is to the data terminal of the elastic memory 16. The other branched received digital signal passes through a delay circuit 26 having a delay amount of 1/2f and is then sent to the write clock terminal C of the elastic memory IJ16.
It is input to K. The terminal device clock is input from the terminal 17 to the read clock terminal of the elastic memo IJ 16, and a reproduced digital signal of frequency f synchronized with the terminal device clock is outputted from the data read terminal to the output terminal 18.

第2図に第1図に示した構成の動作時における各部の信
号の流れを例示する。例えば第2図Aに示す“0”、“
1″の2値符号はディジクル信号源22からビット速度
fの2値ディジタル信号(第2図B)として出力される
。このディジタル信号はコード変換器23で3倍のビッ
ト速度のディジタル信号に変換される。この実施例では
“0”は“10o”に11′は110”に変換される。
FIG. 2 illustrates the flow of signals in each part during operation of the configuration shown in FIG. 1. For example, "0", "
The binary code of 1'' is outputted from the digital signal source 22 as a binary digital signal (FIG. 2B) with a bit rate f.This digital signal is converted by the code converter 23 into a digital signal with a bit rate 3 times higher. In this embodiment, "0" is converted to "10o" and 11' is converted to "110".

この3fのディジクル信号は伝送路24へ送出され、受
信側で増幅器12で増幅される。この増幅器12の出力
は第2図りに示すように、伝送路24による遅延はある
がコード変換器23の出力と同一である。この増幅器1
2の出力はエラスチックメモIJ16のデータ端子りに
入力される。
This 3f digital signal is sent to the transmission path 24 and amplified by the amplifier 12 on the receiving side. As shown in the second diagram, the output of this amplifier 12 is the same as the output of the code converter 23, although there is a delay due to the transmission line 24. This amplifier 1
The output of 2 is input to the data terminal of the elastic memo IJ16.

遅延回路26により1/2fの遅延を受けた信号は第2
図已に示すようになり、これが書込みクロック端子CK
に入力される。この第2図Eに示すディジタル信号の立
上り(又は立下り)をエラスチックメモIJ16の書込
みトリガとする。従ってエラスチックメモ1J16のn
、  (n + 1)、 −(n + 5)番地には第
2図Fに示す内容が書き込まれる。この書込まれた内容
は第2図Gに示す端局装置クロックを読出しクロック端
子17に入力して読出す、この結果第2図Gに示すよう
に端局装置クロックに同期した環ディジタル信号(第2
図B)の再生信号が出力端子18より出力される。
The signal delayed by 1/2f by the delay circuit 26 is
As shown in the figure, this is the write clock terminal CK.
is input. The rise (or fall) of the digital signal shown in FIG. 2E is used as a write trigger for the elastic memory IJ16. Therefore, Elastic Memo 1J16 n
, (n+1), -(n+5) are written with the contents shown in FIG. 2F. This written content is read out by inputting the terminal device clock shown in FIG. 2G to the readout clock terminal 17. As a result, as shown in FIG. Second
The reproduced signal shown in FIG. B) is output from the output terminal 18.

第3図に第2図Bのディジタル信号を第2図Cの3倍ビ
ット速度のディジクル信号に変換するコード変換器23
の構成例を示す、ディジタル信号入力端子31から第4
図Aに示すビット速度rの2値ディジタル信号はAND
回路32の一方の入力端子へ供給される。一方、クロッ
ク入力端子33から、第4l8に示すようにデユーティ
1/3の周期1/fのクロック信号がOR回路34へ供
給されると共に遅延回路35で1/(3f)遅延され、
第4図Cに示すクロック信号としてへNO回路32の他
方の入力端子へ供給される。 AND回路32の出力は
第4図りに示すようになり、この出力はOR回路34に
供給される。この結果、OR回路34の出力に“O”は
“100”、“1”は“110”にそれぞれ3倍ビット
の速度を持つ信号に変換されたものが得られる。
FIG. 3 shows a code converter 23 that converts the digital signal of FIG. 2B into a digital signal of triple the bit rate of FIG. 2C.
, the digital signal input terminal 31 to the fourth
The binary digital signal with bit rate r shown in Figure A is AND
It is supplied to one input terminal of circuit 32. On the other hand, a clock signal with a duty of 1/3 and a period of 1/f is supplied from the clock input terminal 33 to the OR circuit 34 as shown in 4l8, and is delayed by 1/(3f) in the delay circuit 35.
The clock signal shown in FIG. 4C is supplied to the other input terminal of the NO circuit 32. The output of the AND circuit 32 is as shown in the fourth diagram, and this output is supplied to the OR circuit 34. As a result, "O" is converted to "100" and "1" is converted to "110" at the output of the OR circuit 34, which are converted into signals having three times the bit speed.

コード変換器23での変換は直列3ビットの“Onと“
1”とのコードであり、かつ、1/(2f)だけ位相を
ずらした時に、その予め決めた“ビのエツジが環ディジ
タル信号の“0”の変換コードは“0“の中央に位置し
、環ディジタル信号の“1″の変換コードは“1”の中
央に位置するものであればよい。
The code converter 23 converts 3 bits of serial “On” and “
1”, and when the phase is shifted by 1/(2f), the edge of the predetermined “B” will be located in the center of the “0” conversion code of the ring digital signal. , the conversion code for "1" of the ring digital signal may be one located in the center of "1".

例えば第5図Aに示す環ディジタル信号に対し、その“
O”は(010)に、“1”は(011)に変換しても
よく、その場合の変換ディジタル信号は第5図Bに示す
ようになる。この変換ディジタル信号を17(3f)だ
け遅らせた信号は第5図Cに示すようになり、その立上
りで第5図Bの信号を取込めば第5図りに示すように環
ディジタル信号(第5図A)が得られる。
For example, for the ring digital signal shown in FIG.
"O" may be converted to (010) and "1" may be converted to (011), and the converted digital signal in that case will be as shown in Figure 5B.This converted digital signal is delayed by 17 (3f). The resulting signal becomes as shown in FIG. 5C, and if the signal in FIG. 5B is captured at its rising edge, a ring digital signal (FIG. 5A) is obtained as shown in FIG.

あるいは第5図已に示すように第5図Aの0“を(00
1)に、“1”を(011)にそれぞれ変換してもよく
、この信号を第5図Fに示すように1/(3f)遅延し
、その立上りで第5図已に示す信号を取込むと、第5図
Gに示すようになる。この第5図Gは第5図Aの環ディ
ジタル信号に対し、“0″は短く、′ビは長くなるがエ
ラスチックメモリ16に取込んだ状態は前述の二つの例
と同一となり、同様に端局装置のクロックに同期した環
ディジタル信号を得ることができる。
Alternatively, as shown in Figure 5, 0'' in Figure 5A is (00
1), "1" may be converted to (011), and this signal is delayed by 1/(3f) as shown in Figure 5F, and the signal shown in Figure 5A is taken at the rising edge. When loaded, it becomes as shown in Fig. 5G. In FIG. 5G, with respect to the ring digital signal in FIG. 5A, "0" is short and 'B' is long, but the state taken into the elastic memory 16 is the same as the two examples described above, and the end is also the same. A ring digital signal synchronized with the clock of the station equipment can be obtained.

なお環ディジタル信号の各ビットを3倍ではなく、4倍
以上の速度にし、その変換コード中にそれぞれ1つの立
上り及び立下り部分を作り、かつその変換コードのビッ
ト周期X (n + 1/2) (nは正整数)だけ遅
延した時に、環ディジタル信号の“Onについては変換
コードの立上り又は立下りが遅延しないものの“0′に
位置し、環ディジタル信号の11“については変換コー
ドの立上り又は立下りが遅延しないものの“1″に位置
するようにすればよい。このようにして更に各種のコー
ド変換が可能になり、かつ遅延回路26の遅延量も各種
の値に選定することができる。しかし伝送路上でのビッ
ト速度をなるべく低くする点からは3ビットのコードに
変換することが好ましい。
It should be noted that each bit of the ring digital signal is made four times faster than three times faster, one rising and one falling part are created in the converted code, and the bit period of the converted code is X (n + 1/2 ) (where n is a positive integer), for "ON" of the ring digital signal, the rise or fall of the conversion code is not delayed but is located at "0", and for "11" of the ring digital signal, the rise or fall of the conversion code is delayed. Alternatively, it may be positioned at "1" even though the falling edge is not delayed.In this way, various code conversions are possible, and the delay amount of the delay circuit 26 can also be selected to various values. However, in order to reduce the bit rate on the transmission path as much as possible, it is preferable to convert to a 3-bit code.

「発明の効果」 以上説明したようにこの発明のディジタル通信方式では
、受信側でタンク回路やスライス増幅器が不要となり受
信機が簡略な構成になり、また、遅延回路の遅延量も1
/2fと固定であり、従来のように単品ごとに調整を行
う必要がない。なお伝送速度は3倍になるが、光フアイ
バ伝送方式を使用すれば帯域が非常に広いので問題はな
い。
"Effects of the Invention" As explained above, the digital communication system of the present invention eliminates the need for tank circuits and slice amplifiers on the receiving side, resulting in a simpler configuration of the receiver, and the delay amount of the delay circuit is reduced to 1.
/2f is fixed, so there is no need to make adjustments for each item as in the past. Although the transmission speed will be tripled, this will not be a problem if the optical fiber transmission method is used because the bandwidth is very wide.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの発明によるディジタル通信方式の一例を示
すブロック図、第2図はその動作の説明に供する各部の
信号を示すタイムチャート、第3図はコード変換器23
の一具体例を示す論理回路図、第4図は第3図の動作を
説明するための各部の信号の流れを示すタイムチャート
、第5図はこの発明の他の例を示す信号の流れを示すタ
イムチャート、第6図は従来のディジタル通信方式にお
ける受信側の構成を示すブロック図である。 11・・・受信側入力端子、12・・・増幅器、16・
・・エラスチックメモリ、17・・・読出しクロック入
力端子、18・・・出力端子、21・・・送信側、22
・・・ディジタル信号源、23・・・コード変換器、2
4・・・伝送路、25・・・受信側、26・・・遅延回
路。
FIG. 1 is a block diagram showing an example of a digital communication system according to the present invention, FIG. 2 is a time chart showing signals of each part to explain its operation, and FIG. 3 is a code converter 23.
FIG. 4 is a time chart showing the signal flow of each part to explain the operation of FIG. 3, and FIG. 5 shows the signal flow showing another example of the present invention. The time chart shown in FIG. 6 is a block diagram showing the configuration of the receiving side in a conventional digital communication system. 11... Receiving side input terminal, 12... Amplifier, 16...
...Elastic memory, 17...Read clock input terminal, 18...Output terminal, 21...Transmission side, 22
...Digital signal source, 23...Code converter, 2
4... Transmission line, 25... Receiving side, 26... Delay circuit.

Claims (1)

【特許請求の範囲】[Claims] (1)送信側でビット速度fの“0”と“1”の2値デ
ィジタル信号を、その“0”が1ビットの“1”を含む
直列3ビットコードに、“1”が連続した2ビットの“
1”を含む直列3ビットコードであり、かつ変換コード
は“0”にて接続されるビット速度3fのディジタル信
号にコード変換器で変換し、その変換されたディジタル
信号を伝送し、 受信側で受信ディジタル信号に変換して2つに分岐し、
その一方の信号をエラスチックメモリのデータ端子に供
給し、他方の信号を1/2f時間遅延させて、前記エラ
スチックメモリの書き込みクロック端子に入力し、その
クロック端子の信号の立上りもしくは立下りをエラスチ
ックメモリの書込みトリガとするディジタル通信方式。
(1) On the transmitting side, a binary digital signal of “0” and “1” at a bit rate f is converted into a serial 3-bit code in which each “0” contains one bit of “1”. Bit “
It is a serial 3-bit code containing 1", and the conversion code is converted into a digital signal with a bit rate of 3f connected at 0, the converted digital signal is transmitted, and the receiving side Converts to received digital signal and branches into two,
One of the signals is supplied to the data terminal of the elastic memory, the other signal is delayed by 1/2f time and inputted to the write clock terminal of the elastic memory, and the rising or falling edge of the signal at the clock terminal is applied to the elastic memory. A digital communication method that uses a write trigger.
JP60095030A 1985-05-02 1985-05-02 Digital communication system Pending JPS61253958A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60095030A JPS61253958A (en) 1985-05-02 1985-05-02 Digital communication system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60095030A JPS61253958A (en) 1985-05-02 1985-05-02 Digital communication system

Publications (1)

Publication Number Publication Date
JPS61253958A true JPS61253958A (en) 1986-11-11

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP60095030A Pending JPS61253958A (en) 1985-05-02 1985-05-02 Digital communication system

Country Status (1)

Country Link
JP (1) JPS61253958A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008311829A (en) * 2007-06-13 2008-12-25 Seiko Npc Corp Single-wire system data communication method and data communication apparatus

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5913450A (en) * 1982-07-14 1984-01-24 Fujitsu Ltd Method for transmitting series data
JPS5970062A (en) * 1982-10-13 1984-04-20 Fujitsu Ltd Transferring method of data

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5913450A (en) * 1982-07-14 1984-01-24 Fujitsu Ltd Method for transmitting series data
JPS5970062A (en) * 1982-10-13 1984-04-20 Fujitsu Ltd Transferring method of data

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008311829A (en) * 2007-06-13 2008-12-25 Seiko Npc Corp Single-wire system data communication method and data communication apparatus

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