JPS61253958A - Digital communication system - Google Patents

Abstract

PURPOSE:To make a signal synchronize with a clock generated from a terminal equipment with a comparatively simple constitution by converting respective bits of a binary digital signal consisting of '0' and '1' into the 1st and 2nd serial 3-bit codes in accordance with the '0' and '1' on the transmitting side. CONSTITUTION:On the transmitting side 21, a binary digital signal consisting of '0' and '1', having 1/f bit period and outputted from a digital signal source 22 is converted into the 1st and 2nd serial 3-bit codes in accordance with the '0' and '1' by a code converter 23 and the 1st and 2nd 3-bit codes are sent to a transmission line 24. A digital signal of 3f inputted to an input terminal 11 is amplified by an amplifier 12 and branched into two signals and one branched signal is inputted to an elastic memory 16. The other branched signal is inputted to the writing clock terminal CK of the elastic memory 16 through a delay circuit 26 having 1/2f delay. A clock from a terminal equipment is inputted from a terminal 17 to the reading clock terminal of the elastic memory 16 and a digital signal of frequency (f) which is regenerated synchronously with the terminal equipment clock is outputted to an output terminal 18.

Description

DETAILED DESCRIPTION OF THE INVENTION "Field of Industrial Application" The present invention relates to a digital communication transceiver with a simple configuration.

"Prior Art" In the digital communication system, since quadruplexing is performed in the terminal device, it is necessary to synchronize the signal received by the terminal device with the clock of the terminal device. For this reason, conventional digital communication receivers have been constructed as shown in FIG. That is, the digital signal received at the input terminal 11 is amplified by the amplifier 12 and then branched into two signals, one of which is input to the tank circuit 13 . The tank circuit 13 generates a sine wave signal having the same period as the bit rate of the input digital signal, the sine wave signal is shaped into a rectangular wave signal by the slice amplifier 14, and the rectangular wave signal is passed through the delay circuit 15. , the rise of the rectangular wave signal is adjusted so as to substantially coincide with the center of the pulse width of the other branched signal. The adjusted rectangular wave signal and the other branched digital signal are input to the write clock terminal CK and data input terminal of the elastic memory 16, respectively. The clock of the terminal equipment is given to the elastic memory 16 from the terminal 17, and this is successively outputted, and the clock is sent to the output terminal 1.
At step 8, a received digital signal synchronized with the clock of the terminal device is obtained.

“Problem to be solved by the invention” However, in this conventional configuration, the received digital signal is “0”.
Alternatively, if "1" continues, there is no frequency component in the received digital signal that is the same as the bit rate, and even if the received digital signal is input to the tank circuit 13, there is a drawback that a sine wave signal cannot be reproduced.

To solve this problem, CMI and DM convert the signals "0" and "1' into double bit rate signals so that they become alternating "01" and "00" or "11" respectively.
I code is used. However, even if this improvement plan such as the C old code is used, the tank circuit 13 and the slice amplifier 14 are still required, the circuit configuration is complicated, and when synchronizing with the received digital signal in the elastic memory 16. Furthermore, since there are individual variations in the tank circuit 13 and the slice amplifier 14, there is also the drawback that the phase delay amount of the delay circuit 15 must be adjusted for each device, which is time-consuming.

An object of the present invention is to provide a digital communication system that allows synchronization with the clock of a terminal device with a relatively simple configuration.

"Means for Solving the Problem" According to the present invention, a binary digital signal of "0" and "1" is converted to "0" for each bit on the transmitting side.

"1" indicates the first . second 3
Converted to bit code. These first and second 3-bit codes consist of ``0'' and 1'', respectively, and when the ring digital signal is delayed by 1/2 bit period, one predetermined edge of 1'' becomes the The 3-bit code for 1 corresponds to ``0'' before the delay, and the second 3-bit code corresponds to ``1'' before delay.In other words, the first 3-bit code corresponds to ``1'' for 1 bit. Yes, the second 3-bit code has two consecutive "1" bits, and when the converted code is continuous according to the original digital signal, the adjacent codes are connected by "1' and "0". .

This code-converted digital signal is branched into two on the receiving side, one of which is delayed by 1/2 bit period of the ring digital signal, and branched at a predetermined "1" edge of the delayed digital signal. Write the other digital signal to elastic memory.

"Embodiment" FIG. 1 shows an embodiment of the digital communication system according to the present invention. On the transmitting side 21, a binary digital signal of "0" and "1" with a bit period of 1/f is sent from a digital signal source 22. The code converter 23 converts it to “0”.

1 in series, respectively. It is converted into a second 3-bit code, and this converted digital signal of frequency 3f is sent to the transmission path 24.

The 3f digital signal input to the input terminal 11 on the receiving side 25 is amplified by the amplifier 12 and then branched into two, one of which is input as is to the data terminal of the elastic memory 16. The other branched received digital signal passes through a delay circuit 26 having a delay amount of 1/2f and is then sent to the write clock terminal C of the elastic memory IJ16.
It is input to K. The terminal device clock is input from the terminal 17 to the read clock terminal of the elastic memo IJ 16, and a reproduced digital signal of frequency f synchronized with the terminal device clock is outputted from the data read terminal to the output terminal 18.

FIG. 2 illustrates the flow of signals in each part during operation of the configuration shown in FIG. 1. For example, "0", "
The binary code of 1'' is outputted from the digital signal source 22 as a binary digital signal (FIG. 2B) with a bit rate f.This digital signal is converted by the code converter 23 into a digital signal with a bit rate 3 times higher. In this embodiment, "0" is converted to "10o" and 11' is converted to "110".

This 3f digital signal is sent to the transmission path 24 and amplified by the amplifier 12 on the receiving side. As shown in the second diagram, the output of this amplifier 12 is the same as the output of the code converter 23, although there is a delay due to the transmission line 24. This amplifier 1
The output of 2 is input to the data terminal of the elastic memo IJ16.

The signal delayed by 1/2f by the delay circuit 26 is
As shown in the figure, this is the write clock terminal CK.
is input. The rise (or fall) of the digital signal shown in FIG. 2E is used as a write trigger for the elastic memory IJ16. Therefore, Elastic Memo 1J16 n
, (n+1), -(n+5) are written with the contents shown in FIG. 2F. This written content is read out by inputting the terminal device clock shown in FIG. 2G to the readout clock terminal 17. As a result, as shown in FIG. Second
The reproduced signal shown in FIG. B) is output from the output terminal 18.

FIG. 3 shows a code converter 23 that converts the digital signal of FIG. 2B into a digital signal of triple the bit rate of FIG. 2C.
, the digital signal input terminal 31 to the fourth
The binary digital signal with bit rate r shown in Figure A is AND
It is supplied to one input terminal of circuit 32. On the other hand, a clock signal with a duty of 1/3 and a period of 1/f is supplied from the clock input terminal 33 to the OR circuit 34 as shown in 4l8, and is delayed by 1/(3f) in the delay circuit 35.
The clock signal shown in FIG. 4C is supplied to the other input terminal of the NO circuit 32. The output of the AND circuit 32 is as shown in the fourth diagram, and this output is supplied to the OR circuit 34. As a result, "O" is converted to "100" and "1" is converted to "110" at the output of the OR circuit 34, which are converted into signals having three times the bit speed.

The code converter 23 converts 3 bits of serial “On” and “
1”, and when the phase is shifted by 1/(2f), the edge of the predetermined “B” will be located in the center of the “0” conversion code of the ring digital signal. , the conversion code for "1" of the ring digital signal may be one located in the center of "1".

For example, for the ring digital signal shown in FIG.
"O" may be converted to (010) and "1" may be converted to (011), and the converted digital signal in that case will be as shown in Figure 5B.This converted digital signal is delayed by 17 (3f). The resulting signal becomes as shown in FIG. 5C, and if the signal in FIG. 5B is captured at its rising edge, a ring digital signal (FIG. 5A) is obtained as shown in FIG.

Alternatively, as shown in Figure 5, 0'' in Figure 5A is (00
1), "1" may be converted to (011), and this signal is delayed by 1/(3f) as shown in Figure 5F, and the signal shown in Figure 5A is taken at the rising edge. When loaded, it becomes as shown in Fig. 5G. In FIG. 5G, with respect to the ring digital signal in FIG. 5A, "0" is short and 'B' is long, but the state taken into the elastic memory 16 is the same as the two examples described above, and the end is also the same. A ring digital signal synchronized with the clock of the station equipment can be obtained.

It should be noted that each bit of the ring digital signal is made four times faster than three times faster, one rising and one falling part are created in the converted code, and the bit period of the converted code is X (n + 1/2 ) (where n is a positive integer), for "ON" of the ring digital signal, the rise or fall of the conversion code is not delayed but is located at "0", and for "11" of the ring digital signal, the rise or fall of the conversion code is delayed. Alternatively, it may be positioned at "1" even though the falling edge is not delayed.In this way, various code conversions are possible, and the delay amount of the delay circuit 26 can also be selected to various values. However, in order to reduce the bit rate on the transmission path as much as possible, it is preferable to convert to a 3-bit code.

"Effects of the Invention" As explained above, the digital communication system of the present invention eliminates the need for tank circuits and slice amplifiers on the receiving side, resulting in a simpler configuration of the receiver, and the delay amount of the delay circuit is reduced to 1.
/2f is fixed, so there is no need to make adjustments for each item as in the past. Although the transmission speed will be tripled, this will not be a problem if the optical fiber transmission method is used because the bandwidth is very wide.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a digital communication system according to the present invention, FIG. 2 is a time chart showing signals of each part to explain its operation, and FIG. 3 is a code converter 23.
FIG. 4 is a time chart showing the signal flow of each part to explain the operation of FIG. 3, and FIG. 5 shows the signal flow showing another example of the present invention. The time chart shown in FIG. 6 is a block diagram showing the configuration of the receiving side in a conventional digital communication system. 11... Receiving side input terminal, 12... Amplifier, 16...
...Elastic memory, 17...Read clock input terminal, 18...Output terminal, 21...Transmission side, 22
...Digital signal source, 23...Code converter, 2
4... Transmission line, 25... Receiving side, 26... Delay circuit.

Claims (1)

[Claims] (1) On the transmitting side, a binary digital signal of “0” and “1” at a bit rate f is converted into a serial 3-bit code in which each “0” contains one bit of “1”. Bit “
It is a serial 3-bit code containing 1", and the conversion code is converted into a digital signal with a bit rate of 3f connected at 0, the converted digital signal is transmitted, and the receiving side Converts to received digital signal and branches into two,
One of the signals is supplied to the data terminal of the elastic memory, the other signal is delayed by 1/2f time and inputted to the write clock terminal of the elastic memory, and the rising or falling edge of the signal at the clock terminal is applied to the elastic memory. A digital communication method that uses a write trigger.