KR100204062B1 - Phase arragement apparatus for low speed data frame - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

Frame phase aligner that allows frame phase alignment at low speeds.

2. The technical problem to be solved by the invention

It lowers the frequency of the control signals (EN, RD) input to the phase aligner and serial converter, prevents glitches, and synchronizes the phase shifting and the serial conversion process where the signal is restored to the reference clock (CKr). .

3. Summary of Solution to Invention

Johnson counters 4 and 5, which can generate relatively low frequency address signals, are used, and instead of directly using address signals of counters 4 and 5, 1-bit low frequency control without glitches is used. By using the synchronous phase aligners 8 and 9 and the serial converters 12 and 13 using the signals, a separate data reproduction process is unnecessary.

4. Important uses of the invention

Applied to phase aligners in exchanges or repeaters.

Description

Slow Data Frame Phase Aligner

The present invention aligns the frame phase of the received data with the frame phase of the reference frame signal at a low speed, and requires a separate data reproduction process by using a parallel-to-serial (P / S) converter which is a synchronous multiplexer. Data frame phase aligner.

The present invention relates to digital signal processing for phase-aligning a received data frame phase on an input link with a frame phase of a reference frame signal in a communication system such as an exchange or a repeater.

In a conventional data frame phase aligner, a shifter register (S / P converter) converts received data Di and a reference frame signal FPr in parallel, and then uses an address of a binary counter. By delaying the parallel signals of the received frame to the frame phase (Fr) of the reference frame signal (FPr) and multiplexing them using an asynchronous multiplexer, the frame phase of the received data is aligned with the frame phase of the reference frame signal. Doing.

In this manner, inevitably, because of skew of the high frequency address signal of the binary counter connected to the asynchronous multiplexer, jitter occurs in the output signal of the restored multiplexer, thus requiring an additional data reproduction process.

In the present invention, to solve the above problems without using a separate regenerator, to lower the frequency of the control signal (EN, RD) input to the phase aligner and the serial converter, so that the glitches (Glitch) does not occur In addition, the object of the present invention is to provide a frame phase aligner for synchronizing phase alignment and serial conversion of a signal to a reference clock Ckr.

1 is an input / output signal relationship diagram of a frame phase aligner.

2 is an input / output timing diagram of a frame phase aligner.

3 is a detailed block diagram of a frame phase aligner.

4 is an n / 2 bit Johnson counter input / output timing (n = 8).

5 is a timing diagram of a frame phase aligner.

In order to achieve the above object, the present invention provides a first parallel converter which demultiplexes received data into a parallel signal and outputs the first parallel converter in synchronization with a reception clock according to a first write control signal, and demultiplexes a received reference frame into a parallel signal. A second parallel converter that outputs the first write control signal in synchronization with a reference clock, and a first n / 2 bit that counts and outputs a first frame signal driven and driven by a reception clock provided to the first parallel converter; A synchronous counter, a second n / 2-bit synchronous counter that counts and outputs a second frame signal driven and driven by the reference clock, and an output of the first n / 2-bit synchronous counter; A first write control signal generator for providing a first write control signal to a converter, an output of the second n / 2-bit synchronous counter, and a second write control signal to the second parallel converter; A second write control signal generator to provide a first phase aligner for receiving the output of the first parallel converter and aligning a phase of the received data by synchronizing the reference clock according to a phase control signal and outputting the same; A second phase aligner that aligns the phases of the frames by outputting the output of the synchronous counter to the reference clock according to a phase control signal, and receiving the output of the second n / 2-bit synchronous counter; A phase control signal generator for providing a phase control signal to the sorter, and receiving the phase-aligned received data which is the output of the first phase sorter, storing and converting the converted data into serial data according to a read control signal, and outputting them in synchronization with a reference clock; Receives a phase-aligned frame that is an output of the first serial converter and the second phase aligner, and stores and serializes the data according to a read control signal. In response, a second serial converter for synchronizing and outputting in synchronization with a reference clock, and a read control signal generator for receiving an output of the second n / 2-bit synchronous counter and providing a read control signal to the first and second serial converters. It is characterized by one.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

The present invention is a frame phase aligner 1 having an input / output signal relationship as shown in FIG. 1, and as shown in FIG. 3, a 1-to-n parallel converter (2, 3), n / 2 bits. Johnson counters (4, 5), phase aligners (8, 9), write control signal generators (6, 7), phase alignment control signal generators (10), read signal generators (11), n-to-1 series converters (Parallel-to-Serial Converter; 12, 13).

Looking at the configuration and operation of each component constituting the present invention in detail.

1-to-n Serial-to-Parallel Converters (2,3) receive received data Di respectively input to the input terminal Si in synchronization with clocks CKi and CKr as shown in FIG. As shown in FIG. 5, the reference frame FPr is demultiplexed into n-bit parallel signals Di, _{(n-1: 0) ±} / n and FPr / n, where the signal width is nT, and then inputted to the OE stage. When the signal is 0, it is supplied to the _n- bit parallel output P _{(n-1: 0)} in synchronization with CKi and CKr, respectively. The write control signals WRi and WRr input to the OE stage are phase-locked to the frame signals FPi, _± and FPr input to the clear stage Clr of the Jhonson counters 4 and 5, respectively, and the period is nT. Has a phase relationship shown in FIG.

That is, WRi and WRr become ₀ when the output address signal CP _{(7: 0)} of the counters 4 and 5 is (1E) H, and CP _{(7: 4)} becomes (OF) _H and at the same time Di, _{(n-1: 0) / n} and FPr / n are output as P _{(n-1: 0)} , respectively, in synchronization with clocks CKi and CKr.

The output P _{(n-1: 0)} of the 1-to-n parallel converter 2,3 is correspondingly connected 1-1 to the input D _{(n-1: 0)} of the phase aligners 8,9. In the case of the 1-to-n parallel converter 3, since the frame signal FPr is processed, P1 and P2 except for Po. . The value of., P (n-1) is always 0 and is not used. Only Po is provided to the input D of the phase aligner 9.

The n / 2-bit synchronous Johnson counters 4 and 5 (shown when n is 8) are driven by clocks Cki and Ckr, respectively, and output address signals by FPi and FPr input to the clear stage Clr. CP ₀ , CP ₁ ... . The phase of the period of CP ₇ is synchronized. That is, CP ₀ , CP ₁ , based on FPi and FPr. . . The transition phases of rising edges and falling edges of each of CP ₇ are sequentially delayed by T as shown in FIG. 4, and each period is nT of duty 50%. And, as shown in Figure 4, CP ₀ = , CP ₁ = , CP ₂ = , CP3 = Since it has a complementary phase relationship of, the actual effective address signal number is n / 2 bits. That is, since each of CP ₄ , CP ₅ , CP ₆ , and CP ₇ can be generated using signals CP ₀ , CP ₁ , CP ₂ , CP ₃ , signals of n / 2 bits are used. Connect (CP ₀ , CP ₃ ), (CP ₁ , CP ₄ ) and (CP ₀ , CP ₇ ) to inputs a, b of control signal generators 7, 10, 11, respectively, CP ₂ , CP ₅ , CP ₆ Do not use.

In the process of demultiplexing and restoring the received data, the present invention has improved jitter characteristics compared to the conventional scheme because the output address signals CP ₀ , CP ₁ ,. . . Since the frequency of CP ₇ is reduced to 1 / n compared to the output address signal of the binary counter, when these are used, the control inputs to the control inputs OE, E, LD of 2, 3, 8, 9, 12, 13 are used. The frequencies of the signals WRi, WRr, EN, and RD can also be reduced. In addition, as shown in FIG. Since one or more signals do not change at the same time, only a combination of two different bits can generate a control signal without glitches indicating n timeslots within one period nT.

In the present invention, the phase control and read control signals EN, RD in the period β, δ using (CP ₀ , CP ₃ ), (CP ₀ , CP ₇ ) and WRi using (CP ₁ , CP ₄ ) Create WRr respectively.

The write control signal generators 6,7 are implemented with two-input NAND gates, each input (a, b) connected to the outputs CP ₁ and CP ₄ of the counters 4 and 5, each output Z being It is connected to the OE stage of the parallel converters (2, 3). As shown in Fig. 4, the WRi and WRr, which are output signals of the phase detectors 8 and 9, have a period of nT, and the frame signal FPi inputted to the clear terminal clr of the Jhonson counter 4 and 5, respectively. Each period is phase locked to FPr. That is, the output address signal P _{(7: 0} ) of the counters 4 and 5 becomes ₀ only during the time when (1E) _H , so that P _{(n-1: 0)} and P ₀ of the parallel converters 2 and 3 The value changes and becomes 1 in the rest of (n-1) T intervals to maintain the value.

The phase aligners 8 and 9 are implemented as D-flip flops with the control signal E. When E is 0, the data coming into D is synchronized with the reference clock CKr and outputted as Q. When E is 1, the previous value is maintained. The phase aligner 8 aligns the phases of the parallelized received data D _i , _{(n−1) ±} / n, and another phase aligner 9 aligns the phases of the parallelized reference frame FPr / n. Each output signal Q _{(n-1: 0)} , Q is connected to P _{(n-1: 0)} , P ₀ which are input terminals of the serial converter 12,13.

The phase and read control signal generators 10 and 11 are implemented with two-input NAND gates, each of the inputs a and b having the outputs CP ₀ , CP ₇ , CP ₀ , CP ₃ of the counter 5. ), And each output Z is connected to the E stage, the control stage of the phase aligners 8, 9, and the LD of the series converters 12, 13, respectively. As shown in Fig. 4, the cycles of the output signals EN and RD are nT, and each cycle is phase-locked to the frame signals FPi and FPr inputted to the clear terminal Clr of the Jhonson counter 5. do. That is, the phase control signal EN becomes ₀ during the time when the output address signal CP _{(7: 0)} of the counter 5 is (F0) _H , and at the moment when the value transitions to (78) _H , the phase controller 8, The values of inputs D _{(n-1: 0)} and D ₀ in 9) are phase-aligned and appear in outputs Q _{(n-1: 0)} and Q ₀ , and maintain the value in the remaining (n-1) T intervals. do. On the other hand, the read control signal RD becomes ₀ during the time when the output address signal CP _{(7: 0)} of the counter 5 is (OF) _H , so that the input P _{(n-1: 0)} of the serial converter 12, 13 _is , The value of P ₀ is serially converted and appears in the nT interval. As shown in FIG. 4, the output signals Di, _{(n-1: 0)} / n ', FPr / n' phase-aligned at the phase aligners 8 and 9 by EN are nT / 2 from EN. By the RD having a phase margin, the n-to-1 serial converters 12 and 13 are synchronously serially converted to CKr.

The n-to-1 serial conversion process in the n-to-1 parallel-to-serial converter (12, 13) involves the parallelism of P _{(n-1: 0) in} the nT time interval. Since the signal is uniformly distributed in series, the width of the signal output to So becomes T, which is reduced to 1 / n compared to the signal width of P _{(n-1: 0)} . Accordingly, as shown in FIG. 3, the phase-aligned parallel data D _i , _{(n-1: 0)} / n, parallel, which are commonly synchronized with the reference clock CKr and are input to the parallel inputs P _{(n-1: 0)} and P ₀ . Frame FPr / n is stored in parallel when the read control signal RD inputted to LD is 0, as shown in FIG. 5, and when RD is 1, they are sequentially converted into serial signals Do and FP ₀ having a signal width of T. Output as So For serial converter 13, the value of _{P 1, P 2 ..., P} n-1 , except for P ₀ because the handle frame signal FPr / n of one bit is always kept to zero, does not connected .

In the frame phase aligner proposed in the present invention, as shown in FIG. 2, the phase θ _D of the frame bit Fi of the received data Do at the aligner output is a frame of the reference frame signal FP ₀ . To match the phase θ _FP of the bit Fr. (θ _D (Do = Fi) CKr = θ _FP (FPo = Fr) And the maximum permissible deviation between FPr and FPi with frame phase alignment is (θ _± ) FPr centered around ((n / 2) -1) T Limited to

For example, when n = 8, the maximum allowable deviation is 3T, and the outputs D _i , _{(n-1: 0)} ± / n, FPr / n of the parallel converter 2,3 always overlap each other. The sections α, β will be present.

In the present invention, the output EN of the phase control signal generator 10 input to the LDs of the phase aligners 8 and 9 is set to 0 in the _β section (that is, EN _{θ = β} = 0), D _i , _{Each of (n-1: 0) ±} / n, FPr / n generates phase alignment signals D _i , _{(n-1: 0)} / n ', and FPr / n', which are stably sampled by a common reference clock CKr. Let's do it. If D _i , _(n-1) / n 'and FPr / n' are phase aligned by EN of the phase control signal generator 10, a read control signal generator having nT / 2 and phase margin from the instant of phase alignment of EN The output RD of (11) causes D _i , _{(n-1: 0)} / n, and FPr / n to be synchronized in parallel with the CKr of the serial converters 12 and 13, and then serially converted.

The present invention described above is capable of various substitutions, modifications, and changes without departing from the technical spirit of the present invention for those skilled in the art to which the present invention pertains, and is therefore limited to the above-described embodiments and drawings. It is not.

Therefore, the present invention configured and operated as described above has the following effects.

First, the frame phase alignment scheme devised in the present invention is an output of the control signal generators 10 and 11 connected to the phase aligners 8 and 9 for controlling the phase alignment and the serial converters 12 and 13 for restoring the signal. The low frequency of signals EN and RD and no glitches make it possible to reliably phase align and restore signals at low speeds. Second, the received data and the reference frame for phase aligning are serial converters (12, 13). Until the signal is restored, the operation is performed in synchronization with the reference clock CKr, thereby eliminating the need for a separate signal regeneration process.

Claims (4)

A first parallel converter 2 which demultiplexes the received data into a parallel signal and synchronously outputs the received data in synchronization with the reception clock according to the first write control signal; and demultiplexes the received reference frame into a parallel signal to reference the second write control signal. A first n / 2-bit synchronous type that counts and outputs a second parallel converter 3 that outputs in synchronization with a clock and a first frame signal driven and driven by a reception clock provided to the first parallel converter 2; A counter (4), a second n / 2 bit synchronous counter (5) for counting and outputting a second frame signal driven and driven by the reference clock, and the first n / 2 bit synchronous counter (4); A first write control signal generator 6 that receives an output and provides a first write control signal to the first parallel converter, and an output of the second n / 2-bit synchronous counter 4 that receives the output A second write providing a second write control signal to the converter A first phase aligner 8 for receiving a control signal generator 6, an output of the first parallel converter, and aligning a phase of the received data by synchronously outputting in synchronization with a reference clock according to a phase control signal; The output of the second phase aligner 9 for aligning the phase of the frame by receiving the output of the parallel converter in synchronization with the reference clock according to the phase control signal, and the output of the second n / 2-bit synchronous counter 5 A phase control signal generator 10 which receives a phase control signal to the first and second phase aligners 8 and 9 and phase-received received data which is an output of the first phase aligner 8. Receives and reads a phase-aligned frame, which is an output of the first serial converter 12 and the second phase aligner 9, which are outputted in synchronization with a reference clock by being converted into storage and serial data according to the read control signal. Save and serial data according to control signal The output of the second serial converter 13 and the output of the second n / 2-bit synchronous counter (5) is converted to the reference clock and converted to the output to the first and second serial converter (12, 13) And a read control signal generator (11) for providing a read control signal. 2. The low speed data frame phase aligner of claim 1, wherein each of said first and second write control signal generators (6,7) comprises a two-input NAND gate. 2. The low speed data frame phase aligner of claim 1, wherein each of said first and second phase aligners (8,9) consists of a D flip-flop with a control stage (E). 2. The low speed data frame phase aligner of claim 1, wherein each of the phase control signal generator (10) and the read control signal generator (11) comprises a two-input NAND gate.