JPS60235549A - C-bit synchronism system of nb1c code signal - Google Patents

Abstract

PURPOSE:To attain C-bit synchronization at each (n+1)-bit by converting an nB1C code signal into 1/m in parallel, and using a 2-bit data series suitable among parallel conversion outputs, thereby using a clock frequency-dividing the clock in synchronizing with the nB1C code data into 1/m. CONSTITUTION:A serial/parallel converter 10 (shift register) is operated with a clock in synchronizing with a frequency f0 of an nB1C code data inputted from an input terminal 6 and fetches the nB1C code data of consecutive m-bit. Then the serial/parallel converter 10 outputs the fetched m-bit data in parallel by using a signal subject to 1/m frequency division by a 1/m frequency divider from the clock of the frequency f0. A proper 2-bit output among 1/m parallel conversion outputs of the serial/parallel converter 10 is fed to a 2-input exclusive OR circuit 7. When the output signal of the frequency divider 11 is counted by (n+1)-time, the output is fed to an error detection circuit 8 together with output ''1'' from the exclusive OR circuit 7 and the state that the C-bit synchronizing condition is satisfied is outputted from the circuit 8.

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Technical field of the invention The present invention relates to a C-bit synchronization method for nB1c code signals,
In particular, the present invention relates to a C-bit synchronization method for nB1c code signals that enables the use of low-speed operating elements as synchronous circuit elements.

((7) Background of the Technology Generally, as a digital data transmission method, there is a method in which the receiving side of the slave device extracts a clock signal from the data transmitted from the parent device and synchronizes it with the transmitting side of the parent device. For example, if the transmitted data has a continuous focus of 0" or "1", the clock signal cannot be extracted and the receiving side cannot synchronize with the transmitting side. Therefore, the above-mentioned In order to eliminate the continuity of bit strings of the same information in data, a method of encoding and transmitting the transmitted data is adopted.One method of encoding that eliminates the continuity of bit strings of data is nB1cB1. An encoding method is used. This encoding method inserts data every n bits into the C bit indicating the delimiter. Figure 1 shows an example of the n81c code (
This shows an 8BIC encoding system in which C bits b, b'' are inserted every 8 bits.

As can be seen from the figure, C bits b and b' are bits obtained by inverting the immediately preceding data bits a and a'. Therefore, a break between data bits can always be detected every 8 bits, and it is possible to limit the continuity of the same information in data.

However, in this case, C bits b and b' are not data bits and must be deleted on the receiving side.

Technical means for this already exist, but due to technical limitations, circuit elements that operate at high speed must be used, which complicates the circuit configuration and impedes the implementation of the elements. There is a need for the development of technical means that can solve this problem.

(c) Prior art and problems A conventional C-bit synchronous circuit of this type is as shown in FIG. N81c encoded data is input from terminal 5, and clock CLK extracted from the n81c data is input from terminal 6.

The nB1c code data is input to a two-stage flip-flop (FF) 1.2 operated by a clock CLK.

The outputs of FFI and FF2 are each input to an exclusive OR circuit (EOR) 7. Therefore, the output of the FOR circuit 7 is "1" when two consecutive bits of the nH2O code data have different values (for example, the output of FFI is "1" and the output of FF2 is "O"). In other words, as shown in Figure 1, C bits b, b' are always inverted values of the preceding data bits a, a'', so when C bits b, b' are input to the FFI, the EOR circuit The output of 7 becomes "1". In the error detection circuit 8, the clock from the output of the EOR circuit 7 and the terminal 6 is 1/(
n+1) AND with the clock frequency divided by (n+1) by the frequency divider 4. The output of the 1/(n+1) frequency divider 4 is to output one pulse every (n+1) clock pulses, and the clock synchronized with the frequency of the n81c code data is divided into 1/(n+1).

If the output signal of the 1/(n+1) frequency divider 4 is in phase synchronization with the C bit, the result of AND will always be “1”, but
If the phases are not synchronized, the result of the logical product will not always be "1", but will repeat "0" and "1". Therefore, when the error detection circuit 8 detects that the result of the AND is "0", it sends an error detection signal to the protection circuit 9. Since this error detection signal may be erroneously output due to noise etc., the protection circuit 9 detects the error detection signal from the 1/(n+1) frequency divider 4 by sending the error detection signal for a certain period of time.
A correction signal for shifting the phase of the signal by one bit is sent to the inhibitor 3. The inhibitor 3 removes one clock pulse by receiving the correction signal. Therefore 1/
The output signal of the (n+1) frequency divider 4 is delayed in phase by one clock. By sequentially delaying the phase in this manner, the output signal of the 1/(n+1) frequency divider 4 is brought into phase synchronization with the C bit. And 1/(
n+1) Based on the output signal of the branch divider 4, the C bit is deleted in a subsequent circuit (the circuit shown).

However, in the above configuration, as the transmission speed of the N81C code increases, the frequency of the clock signal input from terminal 6 also increases, and the operating speed of the circuit components also needs to increase, making the circuit expensive. turn into.

Object of the Invention The present invention has been made in view of the drawbacks of the conventional circuit system as described above, and its purpose is to provide a high transmission rate N81C.
It is an object of the present invention to provide a C-bit synchronization method for an nB1c code signal, which can synchronize even the code signal using low operating speed elements.

g) Structure of the invention In order to achieve this object, the method of the present invention uses a frequency divider that divides the clock extracted from the n81c code signal into 1/m in the C-bit synchronization method of the bit-serial nB1c code. and the above n8 according to the output of this frequency divider.
A serial-to-parallel converting means for outputting parallel data obtained by converting a 1c code signal into parallel data having a bit width m, a logic circuit for taking an exclusive OR of two adjacent focused outputs among the outputs of the serial-to-parallel converting means, and the above-mentioned components. a 1/(n+1) frequency divider that further divides the output of the frequency generator into 1/(n+1);
C-bit synchronization is achieved by synchronizing the output signal of the (n+1) frequency divider with the output signal of the logic circuit.

(F) Embodiments of the Invention The present invention will now be described in detail with reference to the accompanying drawings.

FIG. 3 shows an embodiment of the invention. In this embodiment, a serial/parallel converter for converting serial data into m-bit parallel data is connected to the input terminal 5 in FIG.
Connect. The n81c code data is inputted from the input terminal 5 to the serial/parallel conversion circuit IO. Serial-to-parallel converter 10
(shift register) is n81 input from input terminal 6
It operates with a clock synchronized with the frequency f of the C code data, and takes in continuous m bits of N81C code data. Then, the serial-to-parallel converter 10 uses a signal obtained by dividing the clock frequency f to 1/m by the 1/m frequency divider 11.
The captured m-bit data is output in parallel. In other words, the output signal of the serial-to-parallel converter 10 is divided by the 1/m frequency divider 11
Since it is output in synchronization with the output signal of f, its operating speed is equal to the frequency f.

The clock is l/m. 1/ of this serial-parallel converter 10
Appropriate 2-bit outputs of the m parallel conversion outputs are connected to a two-man exclusive OR circuit 7.

Next, a description will be given of how C bit synchronization is achieved under the above configuration.

For convenience of explanation, the case where n is 8 and m is 2 will be explained using FIG. 4 as an example. In Figure 4, the time is also 31. The output data bits of the shift register 10 at ~L4+t are shown. n
The states at times t+-s and L i+4 when the eighth or last data bit in the Blc code signal is shifted into the shift-out bit position of the shift register IQ and the C bit is shifted into the shift-in bit position are as follows. think.

This state appears in the frequency divider 11 in the same state as before.
This occurs when the output signal of is counted (n+1) times. Therefore,
At this time, there is an output of "l" from the l/(n+1) frequency divider 4. Therefore, this output is supplied to the error detection circuit 8 together with the "1" output from the exclusive OR circuit 7, and the C
The circuit 8 outputs that the bit synchronization condition is satisfied.

In response to this output, the C bit deletion process is performed in the same manner as in the prior art.

FIG. 5 shows that the expandability of the present invention, which achieves such C-bit synchronization, is not lost as long as the configuration of the present invention described above is satisfied.

FIG. 5 shows the output data bits of the shift register 10 at each time when m=4, that is, a four-stage shift register is used. In this figure, the 2 points enclosed in the score frame are
It is shown that a suitable one of the hits is supplied to the exclusive OR circuit 7 as the above-mentioned 2-bit output of the shift register 10.

In the above embodiment, the case where n and m are relatively prime has been explained, but by setting n and m to mutually prime values, the C bit appears periodically in each bit of the shift register. Data of any two adjacent bits may be input to the EOR circuit 7. Therefore, it is particularly effective when setting the value of n during the test stage. Furthermore, when m is a common divisor of n, a C hit appears in a specific bit of the shift register, so the focus input to the EOR circuit 7 is fixed.

In this way, the n81c code signal is converted in parallel to 1/m,
By using an appropriate 2-bit data series of the parallel conversion output, C-bit synchronization can be achieved every (n+1) bits using a clock obtained by dividing the clock synchronized with the n81c code data into 1/m. Therefore, it is sufficient that the elements used in the C-bit synchronous circuit can operate at a frequency of fo/m. This also provides ease of circuit implementation. Note that, except for the shift register 10 and the 1/m circuit 11, the circuit configuration in FIG. 3 is the same as the circuit configuration in FIG. 2, so a description thereof will be omitted.

(1) Effects of the Invention As described above, according to the present invention, it is possible to prepare for high-speed transmission by reducing the operating speed of the C-bit synchronous circuit element; You can enjoy the ease of 'JJ', etc.

[Brief explanation of drawings]

Figure 1 is a diagram for explaining the n81c encoding method, Figure 2
The figure shows a conventional C-bit synchronization circuit, Figure 3 shows an embodiment of the present invention, Figure 4 is a diagram for explaining the operation of the embodiment of Figure 2, and Figure 5 shows the invention. FIG. 2 is a diagram for detailed explanation. In the figure, 10 is a shift register, 11 is a 1/m frequency divider, and 7
is an exclusive OR circuit, 3 is an inhibitor, and 4 is 1/(n
+1) frequency divider, 8 is an error detection circuit. Patent Applicant Fujitsu Limited Agent Patent Attorney Examination Hiroshi Department Figure 1 Figure 2

Claims (1)

[Claims] In the C-bit synchronization method of the bit-serial nB1c code, there is a frequency divider that divides the clock extracted from the nB1c code signal into 1/m, and the n81c code signal is divided into bits according to the output of this frequency divider. A serial-to-parallel conversion means for outputting parallel data parallel-converted to a width m, a logic circuit for taking an exclusive OR of two adjacent focused outputs among the outputs of the serial-to-parallel conversion means, and an output from the frequency divider. moreover(
and a 1/'(n+1) frequency divider that divides the frequency by 1/n+1), and C bit synchronization is achieved by synchronizing the output signal of the 1/(n+1) frequency divider with the output signal of the logic circuit. The C of the nB1c code signal is characterized in that it takes
Bit synchronization method.