JP2888189B2 - Demultiplexer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
The present invention relates to a demultiplexer (DEMUX) used in a high-density communication system, and more particularly to a demultiplexer configured by stacking a plurality of 1: 2 demultiplexer circuits in a tree shape.

[0002]

2. Description of the Related Art In recent years, with an increase in the amount of information, a high-speed and high-density communication system such as an optical communication system has been devised, and is in the stage of practical use. In this system, since signals of a plurality of information processing subsystems are multiplexed and transmitted through a single signal line, a multiplexer for multiplexing data and a demultiplexer for separating the multiplexed data as before are provided. Required. As the amount of information increases, the speed of serial transmission is required to be high speed,
Developments for improving the speed performance of the multiplexer and the demultiplexer have been promoted. For example, JP
One example is shown in Japanese Patent Application Laid-Open No. 97329.

FIG. 7 shows a typical example of a conventional 1: 8 demultiplexer circuit. 1 is an input signal terminal, 2, 3,
4 is a 1: 2 demultiplexer, and 8, 9, and 10 are 1/2 frequency dividers for generating clock frequency-divided signals. This demultiplexer uses a 1: 2 demultiplexer, and 1:
It is constructed in a tree-like configuration so as to be branched at a ratio of 2 and expanded up to 1: 8. A 1: 2 ^N demultiplexer can be constructed in the same manner as in this case.

The demultiplexer having the configuration shown in FIG. 7 gradually delays by a delay of the circuit as data is separated into 1: 2, 1: 4, and 1: 8. 1/2, 1/4, 1 /
It was necessary to precisely control the timing between the eight clock signals.

Conventionally, such timing control between clock signals is controlled by using delay circuits 16 to 21 such as a multi-stage inverter array for a divided clock signal as shown in FIG. Was. The operation state at this time will be described with reference to the timing chart of FIG.

A positive output signal of the second-stage frequency divider 9 for generating a clock signal is represented by a waveform (q), and the waveform after the waveform (q) has passed through the delay circuit 18 becomes a waveform (r). Since the positive output signal of the 1: 2 demultiplexer 3 in the second stage is output in synchronization with the rising of the clock signal (r), it is represented by a waveform (s).

On the other hand, the positive output signal of the third-stage frequency divider 10 is
It is output as a waveform (t) in synchronization with the rise of the positive output (q) of the second-stage frequency divider.

In order to secure sufficient operation margin and capture data without causing a signal error, it is desirable that a change in the capture of the clock signal occurs at the center of the data pulse of the input signal (s) of the demultiplexer 4. . For this purpose, it is necessary to shift the phase of (t) until the rising portion s ′ of the clock signal (t) comes to the center of the data pulse (s).

In order to perform this timing control, the phase of the waveform (t) is delayed with the delay circuit 20 interposed therebetween, and the waveform (u) is
Is the clock input signal of the demultiplexer 4, the clock waveform (u) changes at the center of the data pulse (s), so that the operation margin can be sufficiently secured.

As described above, the conventional demultiplexer requires some delay circuit for controlling the phase of the clock signal.

[0011]

However, in the above-described conventional demultiplexer structure, the power consumption increases by the amount of the delay circuit for timing control, and furthermore, the characteristic fluctuation of each element constituting the circuit varies. As a result, the delay time of the delay circuit fluctuates, so that the phase between the clocks changes without an appropriate delay, and there is a problem that the operation margin of the demultiplexer is reduced.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a demultiplexer having a configuration in which 1: 2 demultiplexer circuits are stacked in a tree shape to reduce the influence of delay time fluctuation of a delay circuit due to fluctuations in element characteristics and to reduce the phase of a clock signal. An object of the present invention is to provide a demultiplexer which can control and sufficiently secure an operation margin.

[0013]

SUMMARY OF THE INVENTION A first demultiplexer of the present invention distributes a multiplexed signal into two signals.
A main circuit unit having a function of separating a multiplexed signal into N channels in a structure in which demultiplexer circuits are stacked in a tree shape; In the 1: N demultiplexer having the circuit section, the clock signal dividing circuit section generates M (2 ^M =
N) T flip-flop, and k of the main circuit portion
(K is an integer of 1 ≦ k ≦ N) The logic of the output of the k-th frequency divider that generates the clock input signal of the 1: 2 demultiplexer of the stage is inverted, and It is characterized by inputting.

According to a second demultiplexer of the present invention, the frequency divider constituting the clock frequency divider of the demultiplexer according to the first aspect of the present invention comprises a circuit for generating both positive and negative phase signal outputs, and includes k stages. It is characterized in that both the output signals of the positive and negative frequency dividers are exchanged and input to the (k + 1) th frequency divider.

In a third demultiplexer according to the present invention, the frequency divider constituting the clock frequency dividing circuit of the demultiplexer according to the first aspect of the present invention comprises a circuit for generating only a single-phase signal. The inverter is added to the output of the frequency divider to invert the logic, and the output signal is input to the (k + 1) th frequency divider.

(Operation) The operation of the demultiplexer circuit of the present invention will be described with reference to the 1: 8 demultiplexer circuit diagram of FIG. 1 and the timing chart of FIG.

The input waveform of the second-stage frequency divider 6 for supplying a clock to the second-stage 1: 2 demultiplexer 3 is shown in FIG.
When shown in (a), the output of the second stage frequency divider is (a)
Are output in synchronization with the rise of the waveform, and the waveform becomes as shown in waveform (b).

At this time, the output waveform of the second stage 1: 2 demultiplexer 3 is output in synchronization with the rising edge of the clock waveform (b), and thus becomes as shown in waveform (c).

On the other hand, the waveform (d) input to the third-stage frequency divider 7 is a signal obtained by inverting the output (b) of the second-stage frequency divider. Therefore, the output waveform (e) of the third-stage frequency divider
Is output in synchronization with the rise of the waveform (d), and the signal changes at a point shifted by 90 degrees from the rise of the clock waveform (b) of the second-stage frequency divider.

Accordingly, the clock signal (e) takes in the center of the input data (c) of the 1: 2 demultiplexer 4 in the third stage, and a wide timing margin can be secured.

In the above operation, the case where data is taken in at the rising edge of the clock signal has been described. However, the timing margin can be similarly secured when data is taken in at the falling edge of the clock signal.

Also, the demultiplexer circuit of the present invention
Since the timing between the divided clock signals as described above can be controlled without using a delay circuit such as an inverter, the number of elements and power consumption are reduced by the amount of the delay circuit.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the demultiplexer of the first invention. This demultiplexer is a 1: 8 demultiplexer circuit configured by stacking 1: 2 demultiplexers in a tree shape, and data is 1: 2, 2: 4, 4: 8 each time data passes through each 1: 2 demultiplexer.
And it is gradually separated. Similarly 1: by stacking two demultiplexer, N is an integer of 2 or more 1: 2 ^N demultiplexer can also be configured.

Here, the operation of the demultiplexer circuit of this embodiment will be described with reference to the 1: 8 demultiplexer circuit diagram of FIG. 1 and the timing chart of FIG.

The input waveform of the second-stage frequency divider 6 for supplying a clock to the second-stage 1: 2 demultiplexer 3 is shown in FIG.
As shown in (a), the output of the second-stage frequency divider 6 is
The signal is output in synchronization with the rising edge of (a), and becomes as shown in waveform (b).

The output waveform of the second stage 1: 2 demultiplexer 3 is output in synchronization with the rising edge of the above-mentioned clock waveform (b), and thus becomes as shown in waveform (c).

On the other hand, the waveform (d) input to the third-stage frequency divider 7 is a signal obtained by inverting the output (b) of the second-stage frequency divider. Therefore, the output waveform (e) of the third-stage frequency divider 7
Is output in synchronization with the rise of the waveform (d), and the signal changes when the output waveform (b) of the second-stage frequency divider shifts by 90 degrees.

Accordingly, the clock signal (e) rises at the center of the input data (c) of the third stage 1: 2 demultiplexer 4. As a result, since the data is taken in at the center of the data pulse, there is no need to erroneously take in the signal, so that a wide timing margin can be secured.

The above operation has been described in connection with the case where data is taken in at the rise of the clock signal. However, the timing margin can be similarly secured when data is taken in at the fall of the clock signal.

FIG. 3 is a block diagram showing an embodiment of the demultiplexer according to the second invention. This demultiplexer circuit is a 1: 8 demultiplexer in which a 1: 2 demultiplexer is formed in a tree-like configuration as in the first invention.
2, 2: 4, 4: 8. Similarly, a 1: 2 ^N demultiplexer is constructed.

In the demultiplexer circuit according to the present embodiment, the frequency divider for generating the clock signal has a circuit configuration capable of outputting both complementary two-phase signals, and the second stage comprising two 1: 2 demultiplexers 3 The connection relationship between the second-stage frequency divider 9 that supplies the clock to the third stage and the third-stage frequency divider 10 that supplies the clock to the third-stage 1: 2 demultiplexer 4 is 2
The positive output 27 of the frequency divider 9 of the stage is connected to the auxiliary input 30 of the frequency divider 10 of the third stage, and the auxiliary output 28 of the frequency divider 9 is connected to the frequency divider 10.
To the positive input 29 of

Next, the operation of the demultiplexer of this embodiment will be described with reference to the timing chart of FIG.

The phase relationship between the positive output waveform (f) of the second-stage frequency divider 9 and the positive input waveform (h) of the third-stage frequency divider 10 is such that the rising portion is shifted by 90 degrees due to the above connection. Become. Therefore, the rising of the positive output waveform (j) of the third-stage frequency divider also rises at a point shifted by 90 degrees from the rising of the positive output (f) of the second-stage frequency divider.
The phase of the complementary output (k) of the frequency divider in the second stage is shifted by 90 degrees from the phase of the complementary output (g) of the frequency divider in the second stage. For this reason,
Considering the timing of the data and the clock signal in the third-stage demultiplexer, the third-stage positive clock (j) is located at the center of the data (l) output in synchronization with the rising edge of the second-stage clock (f). ) Will rise. Therefore, since the data fetch operation is performed at the center of the data pulse, a sufficient timing margin can be secured without causing a signal error. Similarly, with respect to the third stage complementary clock (k), data changes at the center of the data pulse (l), and a sufficient operation margin can be secured.

In the above operation, data is taken in at the rise of the positive clock input and the fall of the complementary clock input. However, the fall of the positive clock input and the rise of the complementary clock input are considered. The timing margin can be secured in the same manner when data is taken in.

FIG. 5 is a block diagram showing an embodiment of the demultiplexer of the third invention. This demultiplexer is also a stacked 1: 8 demultiplexer circuit based on a 1: 2 demultiplexer, similarly to the first and second inventions, and data is transmitted one by one through each 1: 2 demultiplexer. : 2, 2: 4, and 4: 8. Also, a 1: 2 ^N demultiplexer in which N is an integer of 2 or more can be configured.

In the demultiplexer circuit of this embodiment,
The frequency divider that generates each clock signal is configured by a circuit that outputs only a single-phase signal, and controls the phase between the output of the second-stage frequency divider 12 and the output of the third-stage frequency divider 13. The inversion relation of the output logic is controlled by sandwiching the inverter circuit 15 with respect to the output of the second-stage frequency divider.

FIG. 6 is a timing chart in this case. That is, the waveform of the output waveform (m) of the second-stage frequency divider after passing through the inverter is as shown in (n) because the phase is inverted. Since this waveform is input to the third-stage frequency divider, the rising edge (m) of the output waveform (o) of the third-stage frequency divider is 90 degrees. You will stand up from the point of the shift. Therefore, the third-stage clock (o) rises at the center of the input data (p) in the third-stage demultiplexer 4, and the data is taken in at the center of the data pulse. Therefore, there is no fear of erroneously receiving a signal, and a sufficient timing margin can be secured.

The above operation has been described in connection with the case where data is taken in at the rise of the clock signal. However, the timing margin can be similarly secured when data is taken in at the fall of the clock signal.

[0040]

As described above, according to the present invention, a demultiplexer which can control a phase shift of a clock signal while suppressing the influence of a delay time variation by a delay circuit or the like and sufficiently secure an operation margin can be realized. It becomes possible to do. Furthermore, by using the demultiplexer of the present invention,
It can be expected to configure an LSI with reduced number of elements and power consumption.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of a demultiplexer according to the present invention.

FIG. 2 is a timing chart of the first embodiment of the present invention.

FIG. 3 is a block diagram showing a second embodiment of the demultiplexer according to the present invention.

FIG. 4 is a timing chart of a second embodiment of the present invention.

FIG. 5 is a block diagram showing a third embodiment of the demultiplexer according to the present invention.

FIG. 6 is a timing chart of a third embodiment of the present invention.

FIG. 7 is a block diagram showing a basic configuration of a conventional demultiplexer circuit.

FIG. 8 is a timing chart of a conventional demultiplexer circuit.

[Explanation of symbols]

1 input signal 2, 3, 4 1: 2 demultiplexer (1: 2 DEM
UX) 5-13 1/2 frequency divider 14, 15 Inverter circuit section 16-21 Delay circuit section 22, 24, 26, 27, 28, 31, 32 1/2
Divider output 23, 25, 29, 30 1/2
Divider input

Claims (3)

(57) [Claims] Distributing a multiplexed signal into two:
With a structure in which 2 demultiplexer circuits are stacked in a tree shape,
In a 1: N demultiplexer having a main circuit portion having a function of separating a multiplexed signal into N channels and a frequency dividing circuit portion for producing each frequency divided signal to be supplied to the 1: 2 demultiplexer from an input clock signal, The signal dividing circuit generates M (2 ^M =
N) T flip-flop, and k of the main circuit portion
(K is an integer of 1 ≦ k ≦ N) The logic of the output of the k-th frequency divider that generates the clock input signal of the 1: 2 demultiplexer of the stage is inverted, and A demultiplexer characterized by inputting. 2. A frequency divider comprising a circuit for generating a signal output of both positive and negative phases, wherein the output signals of the positive and negative phases of the k-th frequency divider are exchanged and input to the (k + 1) -th frequency divider. The demultiplexer according to claim 1, wherein: 3. The frequency divider comprises a circuit for generating only a single-phase signal. An inverter is added to the output of the k-th frequency divider to invert the logic. 2. The demultiplexer according to claim 1, wherein the input signal is input to a demultiplexer.