JPH0774654A - Multiplex circuit - Google Patents

Abstract

PURPOSE:To speed the multiplication of data by adjusting the timing of clock by using the only output between the master part and the slave part of a T flip-flop operating with the half frequency of data late. CONSTITUTION:The 1st-3rd selector circuits 1-3 and a timing circuit consisting of a T flip-flop master part 4 and a T flip-flop slave part 5. A clock 1/2CK is provided with the frequency which is a half of that of the data late of a signal outputted from the 3rd selector circuit at the final stage. The clock 1/4CKs 1 and 2 have the frequency which is a fourth of the data late. The clock 1/2CK is given from a synchronizing circuit to the reverse input terminal of the clock of the master part 4 and to the clock input terminal of the slave part 5. In short, the timing of clock is adjusted by using the output of the master part 4 of the T flip-flop operating with the frequency which is a half of that of data late and the output of the slave part 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplexing circuit, and more particularly to a high speed multiplexing circuit used in an ultra high speed system.

[0002]

2. Description of the Related Art A multiplexing circuit is a circuit based on the current switching type selector circuit shown in FIG.
And a timing circuit for matching the timing of the clock with the data to be multiplexed.

In such a configuration, it is the timing circuit that determines the maximum operating speed, and in a high-speed multiplexing circuit, the quality of this timing circuit is important. For example, in the case of a 2-to-1 multiplexing circuit, if the timing is adjusted externally, the circuit composed of only the selector circuit operates at the highest speed. However, in the 4-to-1 multiplexing circuit configured by using the three current switching type selector circuits 11 to 13 as shown in FIG. 5, four data 1 to 4 and three clocks 1 / 2CK, 1 / 4CK, 1 / 4CK2
You have to adjust the timing of the seven signals in
Adjustment is extremely difficult when handling high-speed data of about 0 GHz or higher. 4 to 1 with the circuit of FIG. 5 as the final stage
With the above multiplexing circuit, difficulty in clock adjustment is further increased.

On the other hand, a conventional example of a 4-to-1 multiplexing circuit having a timing circuit operating with one clock is shown in FIG. In this circuit, master-slave D flip-flops 24 and 25 are respectively provided between the final stage selector 26 and the preceding two sets of selectors 21 and 22, so that the timing of the clock and data to the final stage selector 26 is matched. However, when the scale of the timing circuit becomes large, the delay time in that portion cannot be ignored, and it is difficult to apply it to high-speed operation.

[0005]

As described above, 4 to 1
In the above multiplexing circuit, when the timing circuit greatly affects the high speed, and the scale of the timing circuit becomes large,
There was a problem that the delay time in that part could not be ignored. The present invention has been made in consideration of the above problems, and an object of the present invention is to provide a multiplexing circuit that enables a higher speed operation.

[0006]

In the multiplexing circuit of the present invention, a first data signal and a second data signal are input, and a first data signal having a frequency of ¼ of a predetermined data rate is input.
1st selector means for alternately outputting the first data signal and the second data signal and a third data signal and a fourth data signal according to the clock signal of Second with a frequency of / 4
Second selector means for alternately outputting the third data signal and the fourth data signal according to the clock signal, and an output of the first selector means and the second selector means.
The output of the selector means is input, and the output of the first selector means and the output of the second selector means are alternated in accordance with a third clock signal having a frequency of 1/2 of the data rate given from the outside. Third selector means for outputting to the first clock signal and the first clock signal as an input,
A master unit of a T flip-flop that outputs the second clock signal according to a fourth clock signal that has an external frequency of 1/2 of the data rate, and the second clock signal as input, And a slave unit of a T flip-flop that outputs the first clock signal according to a fourth clock signal.

The first selector means, the second selector means, and the third selector means may be constructed by using a current switching type selector circuit. The third
Selector means uses the data selected when the third clock is negative as the output of the first selector means, and the data selected when the third clock signal is positive is the second selector means. May be output. Further, as a clock signal for operating the third selector means,
The fourth clock signal may be used.

[0008]

In the multiplexing circuit according to the present invention, a T flip-flop operating at a frequency of 1/2 of the data rate is used as a clock for operating the first and second selector means in the preceding stage of the third selector means. The respective outputs of the master section and the slave section were used.

Since the two outputs are 90 degrees out of phase with each other, the first output from the first selector means is output.
The output signal obtained by multiplexing the second data signal and the output signal obtained by multiplexing the third and fourth data signals output from the second selector means are used for switching the multiplexed data signals. The timings are shifted from each other by a half cycle.

The output signals of the first and second selector means are multiplexed by the third selector means at the final stage which operates at a frequency of 1/2 of the data rate. Therefore, the third selector means outputs the multiplexed data in the order of the first input signal, the third input signal, the second input signal, and the fourth input signal according to the data rate.

In the multiplexing circuit according to the present invention, the clock timing is adjusted only by the outputs of the master section and the slave section of the T flip-flop,
The delay due to the timing circuit composed of the T flip-flop can be ignored, and since the integration scale does not have to be large, it is very effective for high speed operation.

[0012]

Embodiments will be described below with reference to the drawings. FIG. 1 shows a multiplexing circuit according to the first embodiment of the present invention. This multiplexing circuit includes the first to third selector circuits 1
To 3 and a timing circuit including a master unit 4 of the T flip-flop and a slave unit 5 of the T flip-flop. A current switching type selector circuit as shown in FIG. 4 is used for the first to third selector circuits 1 to 3. A clock ½CK, which will be described later, has a frequency that is ½ of the data rate of the signal output from the third selector circuit 3 in the final stage, and the clock ¼CK
CK1 and CK2 have a frequency of 1/4 of the above data rate.

Data 1 and data 3 are given to the first selector circuit 1, data 2 and data 4 are given to the second selector circuit 2, and first data is given to the third selector circuit 3. Signal Q1 composed of data 1 and data 3 multiplexed by selector circuit 1 and signal Q2 composed of data 2 and data 4 multiplexed by second selector circuit 2. of course,
The above data 1 to 4 are all 1/4 of the above data rate.
Is.

A clock 1 / 2CK is supplied to a clock input terminal of the master section 4 and a clock input terminal of the slave section 5 from a synchronizing circuit (not shown), and to a clock input terminal of the third selector circuit 3. Also, this clock 1 / 2CK is applied.

On the other hand, for the clock 1 / 4CK1 to the first selector circuit 1, the output of the slave section 5 is used and the second
The output of the master section 4 is used as the clock 1 / 4CK2 for the selector circuit 2 of FIG.

Here, in FIG. 2, the clock 1 / 2CK, the clock 1 / 4CK1, the clock 1 / 4CK2, the output Q1 of the first selector, the output Q2 of the second selector, and the output Q3 of the third selector are shown. A time chart is shown.

As shown in FIG. 2, the clock 1 / 4CK1 and the clock 1 / 4CK2 are 1/2 of the clock 1 / 2CK.
The clock 1 / 4CK2 is delayed in phase by an amount corresponding to a half cycle T of the clock 1 / 4CK2 from the clock 1 / 4CK2.

The output Q1 of the first selector circuit 1 is
At the rising edge of the clock 1 / 4CK1, the output Q2 of the second selector circuit 2 is selected at the rising edge of the clock 1 / 4CK2, so that they are shifted from each other by a half cycle.

Next, in the third selector circuit 3, when the signal Q1 is selected when the clock 1 / 2CK is negative and the signal Q2 is selected when the clock 1 / 2CK is positive, as shown by Q3 in FIG. In addition, output data in which data 1 to data 4 are multiplexed can be obtained.

The multiplexer circuit of the present invention has been described above. However, if a selector circuit is further provided in the preceding stage of the 4-to-1 multiplexer circuit, an arbitrary 8-to-1 or higher multiplexer circuit can be constructed. You can Since the frequency of the clock given to the selector circuit provided in the previous stage is sufficiently low, the conventional timing circuit is sufficient as the corresponding timing circuit.

In the present invention, 1 / of the data rate is used.
Since the clock timings are matched only by the outputs of the master section 4 and the slave section 5 of the T flip-flop operating at the frequency of 2, the present invention is applied.
When a multiplex circuit of 1 or more is formed, its maximum operating speed can be determined by the operating speed of the selector circuit without being limited by the timing circuit unlike the conventional case.

In addition to this, there is also an advantage that the scale of integration does not need to be increased as compared with the conventional case. Therefore, the multiplexing circuit of the present invention can operate at extremely high speed.

Next, a multiplexing circuit according to the second embodiment of the present invention will be described. FIG. 3 shows a multiplexing circuit according to the present invention. This multiplexing circuit has almost the same configuration as the multiplexing circuit of the first embodiment described above, but is an improvement of the multiplexing circuit of the embodiment of FIG. 1 so that it can operate at higher speed. A clock 1 / 2CK1 input to the clock input terminal of the master unit 4 and the clock input terminal of the slave unit 5, and a clock 1 / 2CK input to the clock input terminal of the third selector circuit 3.
The feature is that 2 and 2 are independent.

Since the operation of the multiplexing circuit of the present embodiment is almost the same as the operation of the multiplexing circuit shown in FIG. 1, detailed description thereof will be omitted here and only different points will be described below. .

Here, the rising of the clock 1 / 4CK1 and the clock 1 / 4CK2 is caused by the master unit 4
Also, due to the characteristics of the slave section 5, as shown in FIG. 2, it is delayed by τ1 with respect to the rising and falling of the clock 1 / 2CK1, respectively. Further, the output Q1 and the output Q2 of the first selector circuit 1 and the second selector circuit 2 are compared with the rising of the clock 1 / 4CK1 and the clock 1 / 4CK2, respectively, depending on the characteristics of the selector circuits 1 and 2. Delay by τ2.

When the data to be handled becomes faster, the total of the delay times τ1 and τ2 may become larger than the cycle T. At this time, if the clock 1 / 2CK1 shown in FIG. 3 is given to the third selector circuit 3 as a clock, there occurs a problem that the timings of the data and the clock are deviated.

However, in the present embodiment, the clock 1 / which compensates for the delay is supplied to the third selector 3.
Since 2CK2 is independently provided, even if the data to be handled becomes faster and the total of the delay times τ1 and τ2 becomes larger than the cycle T, the third selector circuit 3
It is possible to avoid the problem that the timing between the data and the clock is deviated.

As described above, in the multiplexing circuit of this embodiment,
Since the effects of the delay times τ1 and τ2 can be ignored, the maximum operating speed can be determined only by the operating speed of each selector circuit.

In addition to this, there is also an advantage that the scale of integration does not need to be increased as compared with the conventional case. Therefore, the multiplexing circuit of the present invention can operate at extremely high speed.

Of course, a selector circuit may be further provided in the preceding stage of this 4-to-1 multiplexing circuit to configure an 8-to-1 or higher arbitrary multiplexing circuit. The delay compensation may be performed by, for example, appropriately adjusting the length of the cable for the clock 1 / 2CK2, that is, by adjusting the delay time of the cable. Further, the present invention is not limited to the above-described embodiments, and various modifications can be carried out without departing from the scope of the invention.

[0031]

In the multiplexing circuit of the present invention, the clock timing is matched only by the respective outputs of the master section and the slave section of the T flip-flop operating at a frequency of 1/2 of the data rate.

Therefore, when the present invention is applied to construct a multiplexing circuit of 4: 1 or more, the maximum operating speed is determined by the operating speed of the selector circuit without being limited by the timing circuit. Therefore, the delay due to the timing circuit can be ignored and the data can be multiplexed at high speed.

[Brief description of drawings]

FIG. 1 is a diagram showing a multiplexing circuit according to a first embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation timing of the multiplexing circuit of FIG.

FIG. 3 is a diagram showing a multiplexing circuit according to a second embodiment of the present invention.

FIG. 4 is a diagram showing an example of a selector unit of a multiplexing circuit.

FIG. 5 is a diagram showing a 4-to-1 multiplexing circuit composed only of conventional selector circuits.

FIG. 6 is a diagram showing a 4-to-1 multiplexing circuit in which a timing circuit is composed of a conventional D flip-flop.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... 1st selector part 2 ... 2nd selector part 3 ... 3rd selector part 4 ... Master part of T flip-flop 5 ... Slave part of T flip-flop

Claims (1)

[Claims] 1. A first data signal and a second data signal are input, and the first data signal and the second data signal are input according to a first clock signal having a frequency of ¼ of a predetermined data rate. The first selector means for alternately outputting the data signal, the third data signal and the fourth data signal are input, and the third clock signal having a frequency of ¼ of the data rate is input to the third selector. Data signal and the fourth
Second selector means for alternately outputting the data signal, and the output of the first selector means and the output of the second selector means are input, and a frequency of 1/2 of the data rate given from the outside is input. According to the third clock signal having, the output of the first selector means and the second
Third selector means for alternately outputting the output of the selector means, and a fourth clock signal having an input frequency of the first clock signal and having a frequency of 1/2 of the data rate, A master portion of a T flip-flop that outputs a second clock signal, and a T that inputs the second clock signal and outputs the first clock signal according to the fourth clock signal.
A multiplexing circuit comprising a slave unit of a flip-flop.