JPH03121692A - Semiconductor memory for picture processing - Google Patents
Semiconductor memory for picture processingInfo
- Publication number
- JPH03121692A JPH03121692A JP26049589A JP26049589A JPH03121692A JP H03121692 A JPH03121692 A JP H03121692A JP 26049589 A JP26049589 A JP 26049589A JP 26049589 A JP26049589 A JP 26049589A JP H03121692 A JPH03121692 A JP H03121692A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- delay
- luminance signal
- color difference
- delay time
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 9
- 230000001934 delay Effects 0.000 claims abstract description 5
- 239000002131 composite material Substances 0.000 claims description 5
- 238000010586 diagram Methods 0.000 description 3
- 230000000630 rising effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Landscapes
- Processing Of Color Television Signals (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は画像処理用半導体メモリに関し、特に時分割に
入力された、コンポジットビデオ信号をデコードして得
られた輝度信号と色差信号とを並列化して出力する画像
処理用半導体メモリに関する。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor memory for image processing, and in particular, a method for processing in parallel a luminance signal and a color difference signal obtained by decoding a composite video signal input in a time-division manner. The present invention relates to a semiconductor memory for image processing that converts and outputs images.
従来、この種の画像処理用半導体メモリは、第２図に示
すように、時分割に入力された、コンポジットビデオ信
号をデコードして得られた輝度信号と色差信号とを一時
記憶し出力するメモリ回路１と、このメモリ回路１から
の輝度信号ＳＹＩ と色差信号Ｓｃとを並列化してあた
かも同時に入力された信号の様に出力する為に、出力さ
れた輝度信号ＳＹｌと色差信号ＳＣとの時間的なずれを
一定量だけ補正する遅延回路２Ａとを有する構成となっ
ていた。Conventionally, this type of semiconductor memory for image processing, as shown in FIG. 2, is a memory that temporarily stores and outputs a luminance signal and a color difference signal obtained by decoding a composite video signal input in a time-division manner. In order to parallelize the luminance signal SYI and the color difference signal Sc from the circuit 1 and the memory circuit 1 and output them as if they were input at the same time, the time difference between the output luminance signal SYI and the color difference signal SC is The configuration includes a delay circuit 2A that corrects the deviation by a certain amount.
上述した従来の画像処理用半導体メモリは、遅延回路２
Ａによシ補正する遅延時間が固定された構成となってい
るので、遅延回路２Ａの遅延時間が製造条件や外囲条件
等によって最適でない状態になった時に、この遅延時間
を最適になる様に調整することが困難であるという欠点
がある。The conventional semiconductor memory for image processing described above has a delay circuit 2.
Since the delay time corrected by A is fixed, even if the delay time of the delay circuit 2A becomes non-optimal due to manufacturing conditions, surrounding conditions, etc., this delay time can be optimized. The disadvantage is that it is difficult to adjust.
本発明の目的は、遅延回路の遅延時間が最適埴からずれ
た時に、容易に最適値とすることができる画像処理用半
導体メモリを提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory for image processing that can easily set the delay time of a delay circuit to the optimum value when it deviates from the optimum value.
本発明の画像処理用半導体メモリは、コンポジットビデ
オ信号をデコードして得られた輝度信号と色差信号とを
一時記憶し出力するメモリ回路と、外部からの制御信号
によシ制御できる遅延時間をもち前記メモリ回路からの
輝度信号及び色差信号の少なくとも一方を所定の時間だ
け遅延させる遅延回路とを有している。The semiconductor memory for image processing of the present invention has a memory circuit that temporarily stores and outputs a luminance signal and a color difference signal obtained by decoding a composite video signal, and a delay time that can be controlled by an external control signal. and a delay circuit that delays at least one of the luminance signal and color difference signal from the memory circuit by a predetermined time.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第１図は本発明の一実施例を示すブロック図である。FIG. 1 is a block diagram showing one embodiment of the present invention.
この実施例は、コンポジットビデオ信号ラブコードして
得られた輝度信号と色差信号とを一時記憶し出力するメ
モリ回路ｌと、Ｄフリップフロップ２１Ａ、２１８及び
セレクタ２２を備え外部からの制御信号ＣＮＴにより制
御できる遅延時間をもちメモリ回路１からの輝度信号Ｓ
Ｙｌ及び色差信号Ｓｃの一方の輝度信号ＳＹ０を所定の
時間だけ遅延させる遅延回路２とを有する構成となって
いる。This embodiment includes a memory circuit 1 for temporarily storing and outputting a luminance signal and a color difference signal obtained by applying the love code to a composite video signal, D flip-flops 21A and 218, and a selector 22, and is controlled by an external control signal CNT. The luminance signal S from the memory circuit 1 has a controllable delay time.
The configuration includes a delay circuit 2 that delays the luminance signal SY0, which is one of Yl and the color difference signal Sc, by a predetermined time.
メモリ回路１から出力された輝度信号ＳＹＩは、クロッ
ク信号ＣＫの立上りによりＤフリップフロラフ２１Ａか
ら出力され、クロック信号ＣＫの次の立上シでＤクリッ
プフロック２１Ｂから出力される。つまＪＤノリッグフ
ロップ２１Ａの出力端とＤフリップフロック２１Ｂの出
力端とはクロック信号ＣＫの１サイクル分の遅延差があ
シ、セレクタ２２によりこれらＤフリップフロップ２１
Ａ。The brightness signal SYI output from the memory circuit 1 is output from the D flip block 21A at the rising edge of the clock signal CK, and is output from the D clip floe block 21B at the next rising edge of the clock signal CK. There is a delay difference of one cycle of the clock signal CK between the output terminal of the JD Norig flop 21A and the output terminal of the D flip-flop 21B.
A.
２１Ｂの出力信号を切換えることにより輝度信号ＳＹ□
に対する遅延時間を最適になる様に調整することができ
る。By switching the output signal of 21B, the brightness signal SY□
The delay time can be adjusted to be optimal.
この実施例は、２つの遅延時間を切換えるという最も単
純な例を示したものであるが、更に多くのＤフリップ７
０ツブ金設は更に多くの遅延時間を切換えるようにすれ
ば、よシ正確に遅延時間を調整することができる。This example shows the simplest example of switching two delay times, but more D flips 7
The delay time can be adjusted more accurately by switching over more delay times in the zero-tub metal setting.
また、制御信号ＣＮＴで遅延時間を切換えるようにして
いるが、クロック信号ＣＫの周波数を変えることによっ
ても遅延時間を調整することができる。Furthermore, although the delay time is switched using the control signal CNT, the delay time can also be adjusted by changing the frequency of the clock signal CK.
また、輝度信号ＳＹ１に対してのみ遅延回路２を設けた
が、色差信号Ｓ。に対してのみ、又は輝度信号ＳＹ□及
び色差信号Ｓｃの両方に対して遅延回路を設けることも
できる。Further, although the delay circuit 2 is provided only for the luminance signal SY1, the delay circuit 2 is provided only for the luminance signal SY1, but for the color difference signal S. It is also possible to provide a delay circuit only for the luminance signal SY□ or for both the luminance signal SY□ and the color difference signal Sc.
なお、この実施例においては、遅延回路をＤフリップフ
ロップヒセレクタとで構成しているが、その他の遅延素
子、例えばインバータやシフトレジスタ等を使用して構
成することもできる。In this embodiment, the delay circuit is composed of a D flip-flop high selector, but it can also be constructed using other delay elements, such as an inverter or a shift register.
以上説明したように本発明は、外部からの制御信号によ
シ遅延時間を切換えることができる遅延回路を設け、こ
の遅延回路によシ輝度信号及び色差信号の少なくとも一
方を遅延させる構成とすることによシ、輝度信号及び色
差信号に対する遅延時間を容易に最適値とすることがで
きる効果がある。As explained above, the present invention has a configuration in which a delay circuit that can switch the delay time by an external control signal is provided, and this delay circuit delays at least one of the luminance signal and the color difference signal. Another advantage is that the delay times for the luminance signal and color difference signal can be easily set to optimal values.
第１図は本発明の一実施例を示すブロック図、第２図は
従来の画像処理用半導体メモリの一例を示すブロック図
である。
１・・・メモリ回路、２．２Ａ・・・遅延回路、２１Ａ
２１Ｂ・・・Ｄフリップ７０ツブ、２２・・・セレクタ
。FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a block diagram showing an example of a conventional image processing semiconductor memory. 1...Memory circuit, 2.2A...Delay circuit, 21A
21B...D flip 70 knob, 22...Selector.
Claims (1)
号と色差信号とを一時記憶し出力するメモリ回路と、外
部からの制御信号により制御できる遅延時間をもち前記
メモリ回路からの輝度信号及び色差信号の少なくとも一
方を所定の時間だけ遅延させる遅延回路とを有すること
を特徴とする画像処理用半導体メモリ。A memory circuit that temporarily stores and outputs a luminance signal and a color difference signal obtained by decoding a composite video signal, and a memory circuit that has a delay time that can be controlled by an external control signal and outputs at least the luminance signal and color difference signal from the memory circuit. 1. A semiconductor memory for image processing, comprising a delay circuit that delays one side by a predetermined time.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1260495A JP2918927B2 (en) | 1989-10-04 | 1989-10-04 | Semiconductor memory for image processing |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1260495A JP2918927B2 (en) | 1989-10-04 | 1989-10-04 | Semiconductor memory for image processing |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03121692A true JPH03121692A (en) | 1991-05-23 |
| JP2918927B2 JP2918927B2 (en) | 1999-07-12 |
Family
ID=17348762
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1260495A Expired - Fee Related JP2918927B2 (en) | 1989-10-04 | 1989-10-04 | Semiconductor memory for image processing |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2918927B2 (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6331390A (en) * | 1986-07-25 | 1988-02-10 | Canon Inc | Picture memory device |
| JPS6331380A (en) * | 1986-07-25 | 1988-02-10 | Mitsubishi Electric Corp | Magnetic picture recording and reproducing device |
-
1989
- 1989-10-04 JP JP1260495A patent/JP2918927B2/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6331390A (en) * | 1986-07-25 | 1988-02-10 | Canon Inc | Picture memory device |
| JPS6331380A (en) * | 1986-07-25 | 1988-02-10 | Mitsubishi Electric Corp | Magnetic picture recording and reproducing device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2918927B2 (en) | 1999-07-12 |
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