JPH02139957A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To adjust setup time as well as hold time easily from the outside by imputting a plurality of signals of a delay circuit which is connected to the output end of an input buffer and by imputting one of the foregoing signals to an internal circuit by output of a selector through control signals. CONSTITUTION:Input signals from an input terminal 1 is inputted to a selector 19 through an input buffer 24 and then, even the input signals which are delayed by delay circuits 7 and 8 or 7, 8, 9, and 10 as well as 7, 8, 9, 10, 11, and 12 respectively are inputted to the selector 19. Eventually, these signals are data having four kinds of delayed periods. Controlled signals from control terminals 3 and 4 are inputted to the control terminals of the selector 19 through a decoder 21 and one data is selected out of four kinds of them and it is outputted. In the same manner, among signals inputted to an input terminal 2, one signal is selected out of four kinds of data and its signal is outputted. The output powers of selectors 19 and 20 are inputted to respective data terminals and clock terminals of D-F.F 23.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and in particular to a semiconductor integrated circuit configured such that set-up time and hold time between input terminals can be changed by an external control terminal. Regarding circuits.

[Prior Art] FIG. 2 is a circuit diagram showing a conventional semiconductor integrated circuit of this type.

An input buffer 32 is connected to the input terminal 31,
An internal circuit 33 is connected to the output end of the input buffer 32. Therefore, the input signal input to the input terminal 31 is input to the internal circuit 33 via the input buffer 32.

[Problems to be Solved by the Invention] In the conventional semiconductor integrated circuit described above, the setup time and hold time between input terminals are determined at the time of circuit design, so the timing of input signals is adjusted on the printed circuit board. There is. Therefore, if the set-up time or hold time changes due to manufacturing variations in semiconductor integrated circuits, etc., there is a drawback that it is necessary to add a new delay circuit to the printed circuit board to adjust the timing between input signals.

The present invention has been made in view of such problems, and includes:
An object of the present invention is to provide a semiconductor integrated circuit in which the timing between input signals can be adjusted without providing a delay circuit on a printed circuit board, and thereby the setup time and hold time can be easily adjusted.

[Means for Solving the Problems] A semiconductor integrated circuit according to the present invention has an input terminal into which an input signal is input, an input buffer connected to this input terminal, and an input terminal connected to an output terminal of this input buffer and connected to each other. n stages of delay circuits connected in series, a control terminal into which a control signal is input, and m signals obtained by extracting the outputs of the delay circuits for each stage or stages, and A control signal is input from the control terminal, and this control signal causes the m
It is characterized by having a selector that selects and outputs one of the signals, and inputting the output of this selector to an internal circuit.

[Function] In the present invention, an input signal input to an input terminal is input to an n-stage delay circuit via an input buffer, and the output of this delay circuit is taken out for each stage or stages to set different delay times. The input signals are input to the selector as m input signals. A control signal is input to the selector via the control terminal, and one of the m input signals input to the selector is selected and output to the internal circuit. Therefore, the delay time of the input signal output from the selector, ie, the timing of the input signal, can be adjusted by the control signal. Therefore, even if the setup time or hold time of the semiconductor integrated circuit changes due to manufacturing variations or the like, this can be easily adjusted by adjusting the timing between input signals using the control signal.

[Example] Next, an example of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

Input terminal 1 is connected to the input of input buffer 24, and the output of input buffer 24 is connected to delay circuit 7. The delay circuits 7, 8, 9, 10, 11.12 are connected in series in this order, and the input terminal of the delay circuit 7, the output terminal of the delay circuit 12, the connection part between the delay circuit 8 and the delay circuit 9, and The connection portion between the delay circuit 10 and the delay circuit 11 is connected to the selector 1, respectively.
9 are individually connected to the four input terminals of 9. Therefore,
Output of input buffer 24 and delay circuits 8, 10 for every second stage
．． Twelve outputs are input to each input terminal of the selector 19, respectively. Control signals from the control terminals 3 and 4 are input to the decoder 21, decoded, and further input to the selector 19 as control signals.

On the other hand, the input terminal 2 is connected to the input of the input buffer 25, and the output of the input buffer 25 is connected to the delay circuit 13. The delay circuits 13, 14, 15, 16, 17, and 18 are connected in series in this order, and the output of the input buffer 25 and the output of the delay circuits 14, 16, and 18 are connected to the selector 2, respectively.
They are individually input to the four input terminals of 0. Control signals from control terminals 5 and 6 are decoded by decoder 22 and then input to selector 20 .

The output of the selector 19 is input to the data terminal of a delay type (D) flip-flop (hereinafter referred to as D-F-F) 23 as an internal circuit, and the output of the selector 2° is inputted to the data terminal of a delay type (D) flip-flop (hereinafter referred to as D-F-F) as an internal circuit.
It is input to the clock terminal of F23.

In the semiconductor integrated circuit configured in this manner, an input signal from the input terminal 1 is input to the selector 19 via the input buffer 24. Further, the output of the input buffer 24 is also input to the delay circuit 7, and the input signal delayed by the delay circuit 7.8, the input signal delayed by the delay circuits 7, 8, 9.10, and the delay circuits 7, 8. ,9.10,1
The input signal delayed by 1.12 is also input to the selector 19. In the end, the input signal input to the selector 19 is data having four types of delay times, including the input signal directly input from the input buffer 24. The control signal from the control terminal 3.4 is input to the control terminal of the selector 19 via the decoder 21, and the selector 19 selects one of the four types of delay time data input to the input terminal based on this control signal. Select one and output.

Similarly, the input signal at the input terminal 2 is input to the selector 20 as a signal having four types of delay times via the input buffer 25 and the delay circuits 13, 14, 15, 16, and 17. The control signals from the control terminals 5 and 6 are input to the control terminal of the selector 20 via the decoder 22, and the selector 20 is controlled by this control signal and outputs data with four types of delay times input to its input terminal. Select one of them and output it.

The outputs of selectors 19 and 20 are input to the data terminal and tarok terminal of D-F-F 23, respectively.

In this embodiment, if the setup time of the signal input to the input terminal l is not sufficient for the signal input to the input terminal 2, among the four data input to the selector 20 with different delay amounts, Data with a large amount of delay is selected and output from the selector 20. By this, D
-F - The setup time for the clock and data of the F23 can be made sufficient. On the other hand, input terminal 2
If the hold time of the signal at input terminal 1 with respect to the signal of
23 clock and data hold time can be made sufficient.

[Effects of the Invention] As explained above, the present invention connects n stages of delay circuits to the input in series, takes out the output of the delay circuit for each stage or multiple stages, inputs it to the selector, and inputs the output from the control terminal. Since we configured the control signal to select one of these m inputs and output it to the internal circuit, even if variations in characteristics occur during the manufacturing process of semiconductor integrated circuits, there will be no additional delay on the printed circuit board. The timing between input signals can be easily adjusted via a control signal without providing any circuit. Therefore, there is an advantage that the set-up time and hold time can be easily adjusted from the outside.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a semiconductor integrated circuit according to an embodiment of the present invention, and FIG. 2 is a circuit diagram showing a conventional semiconductor integrated circuit. 1.2, 31: input terminal, 3, 4, 5, 6. control terminal,
7.8.9,10,11.12.13゜14.15,1
6, 17, 18. Delay circuit, 19°20: Selector, 2
1.22; Decoder, 23; D-F-F (internal circuit),
24, 25. 32; Input buffer, 33; Internal circuit

Claims (1)

[Claims] (1) An input terminal into which an input signal is input, an input buffer connected to this input terminal, an n-stage delay circuit connected to the output terminal of this input buffer and connected in series, and a control signal. The input control terminal and m signals obtained by extracting the output of the delay circuit for each stage or multiple stages are input, and a control signal is input from the control terminal, and this control signal causes the m 1. A semiconductor integrated circuit comprising: a selector that selects and outputs one of the signals, and the output of the selector is input to an internal circuit.