JPH06324113A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To control a scan pass circuit without providing a control signal line exclusive for scan pass. CONSTITUTION:A semiconductor integrated circuit has a scan signal transmission line for connecting each scan flip flop in series; selecting circuits (120 13, 14) connected to the scan signal transmission line to select the scan signal transmission line or a signal input line from a circuit block other than scan pass with general operation mode and scan mode as the input data to a scan flip slop according to the scan control signal SIN inputted from a scan signal input line 112; and an output circuit 15 connected to the scan signal transmission line to output a scan control signal in the first half period and a scan data in the latter half signal, so that the scan control signal and the scan data can be inputted with a common scan signal transmission line.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit,
In particular, the present invention relates to a semiconductor integrated circuit in which a plurality of flip-flops are connected in series to form a scan path in order to set test data for the semiconductor integrated circuit.

[0002]

2. Description of the Related Art Conventionally, as a semiconductor integrated circuit device of this type, as shown in FIG.
1, 52 ,. ． ． 5n is a scan data transmission line 521,
522 ,. ． ． A scan path is configured by serially connecting via 52n.

Incidentally, in FIG. 5, 331, 33
2 ,. ． ． 33n is a normal data input line, 341, 34
2 ,. ． ． 34n is an output line for normal data, and these are connected to other circuit blocks in the semiconductor integrated circuit (LSI) according to the original circuit configuration of the semiconductor integrated circuit.

Switching between the normal operation mode and the scan mode of the circuit of FIG. 5 is performed by a scan control signal input to the scan control terminal 511. That is, this circuit operates as a shift register in the scan mode, and the scan data input from the scan data input terminal 311 receives the scan data transmission lines 521 and 52.
2 ,. ． ． Scan flip-flop 5 via 52n
1, 52 ,. ． ． It is set to 5n.

After that, the operation mode is switched to the normal operation mode and the flip-flops 51, 52 ,. ． ． 5n data input to the normal data input lines 331, 332 ,. ． ． 33n, and data output to normal data output lines 341, 34
2 ,. ． ． By setting 34n, a circuit connection corresponding to the normal operation of the semiconductor integrated circuit is made, and the semiconductor integrated circuit is tested under the normal operation.

FIG. 4 shows an example of a conventional scan flip-flop circuit. In the circuit of FIG. 4, the selector 12
Is connected to the data input terminal D of the flip-flop 11, and corresponding to the input from the scan control signal line 411, the normal data input 111 is selected in the normal operation and the scan data input 112 is selected in the scan mode.

The data of the flip-flop 11 is output from the data output line 113 in the normal operation and the data output line 114 in the scan mode. A scan path is formed by connecting a plurality of circuits in FIG. 4 in series in the scan data input line 112 and the scan data output line 114.

[0008]

In the circuit having the conventional scan path described above, the scan data input line 112 is used.
In addition to the signal line 111 and the signal line 111, a scan control signal line 411 connected to all scan flip-flops and a control signal input terminal are required. Increase,
As a result, there is a problem that the circuit area of the semiconductor integrated circuit becomes large.

In view of the above problems, it is an object of the present invention to enable control of the scan path circuit without providing a control signal line dedicated to the scan path.

[0010]

In order to solve the above problems, a semiconductor integrated circuit of the present invention includes a scan signal transmission line for serially connecting scan flip-flops and a scan signal input line connected to the scan signal transmission line. A selection circuit for selecting either the scan signal transmission line or a signal input line from a circuit block other than the scan path as input data to the scan flip-flop in the normal operation mode and the scan mode according to the scan control signal input from the line. And an output circuit connected to the scan signal transmission line, which outputs a scan control signal in the first half cycle and outputs scan data in the second half cycle.

[0011]

In the semiconductor integrated circuit of the present invention configured as described above, the scan control signal and the scan data are divided into the first half cycle and the second half cycle, and the common scan signal is supplied to the serially connected scan flip-flops. By enabling input via the transmission line, control using signal lines and signal terminals equivalent to conventional scan data input is possible without providing signal lines and signal terminals for scan path control, reducing the circuit area. Is achieved.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the semiconductor integrated circuit of the present invention will be described below with reference to the drawings. FIG. 1 shows an embodiment of the present invention and is a circuit diagram of a scan flip-flop. In the circuit shown in FIG. 1, a signal line 1 for normal data input DIN
11, and a signal line 113 for normal data output DOUT
Are connected to other circuit blocks in the semiconductor integrated circuit, and are used for data input and data output during normal operation of the semiconductor integrated circuit.

Signal line 112 for scan signal input SIN
Is connected to the scan flip-flop of the previous stage, and the signal line 114 for the scan signal output SOUT is connected to the scan flip-flop of the next stage.

Further, the selector 12 and the flip-flop 1
3. The inverter 14 constitutes a selection circuit that selects the signal line 111 for the normal data input DIN or the signal line 112 for the scan signal input SIN as the data input of the flip-flop 11 in the normal operation mode and the scan mode. .

Further, the selector 15 has a scan output SO
The output value of the signal line 114 for UT is set to the signal line 112 for scan input SIN in the first half cycle and the second half cycle of the clock.
And the data output 117 of the flip-flop 11 are provided respectively.

The operation example of the circuit of FIG. 1 will be described below with reference to FIG. Switching the operation mode of the circuit of FIG.
In the first half cycle of the clock input CKIN, the scan control signal is input to the signal line 112 for the scan signal input SIN. That is, for example, when the scan control signal has the logical value "0", the circuit of FIG. 1 is in the normal operation mode, and when it has the logical value "1", it is in the scan mode.

First, the normal operation mode will be described.
In the normal operation mode, as shown in FIG. 2, in the first half cycle (CKIN = “H”) of the clock input CKIN, the logical value “0” is set as the scan control signal to the signal line 112 for the scan signal input SIN. input.

The scan control signal "0" is taken into the flip-flop 13 at the falling edge of the clock input CKIN, and the selector 12 responds to the data input of the flip-flop 11 in response to the selector control signal 116 from the flip-flop 13. The signal line 111 for normal data input is selected as. This allows clock input C
Normal data is taken into the flip-flop 11 at the rising edge of KIN.

Next, in the scan mode, the logical value "1" is input to the signal line 112 for the scan input SIN as the scan control signal in the first half cycle of the clock input CKIN. The selector 1 corresponds to the scan control signal “1” fetched at the falling edge of the clock input CKIN.
2 selects the signal line 112 for the scan signal input SIN.

As a result, the scan data input to the signal line 112 for the scan signal input SIN in the second half cycle is taken into the flip-flop 11 at the next rising edge of the clock input CKIN.

Scan output SOUT in the circuit of FIG.
In the first half cycle, the selector 15 selects the signal line 112 for the scan input SIN in the first half cycle, and the signal line 117 for the data output of the flip-flop 11 is selected in the second half cycle. As a result, the scan control signal SIN input from the signal line 112 for the scan input SIN is directly transmitted to the scan flip-flop of the next stage in the first half cycle, and Q _{11 of the} flip-flop 11 is transmitted in the second half cycle.
The data output from is transmitted as the shift data of the scan path.

FIG. 3 is an example of a circuit in which a scan path is formed by using the scan flip-flop circuit of FIG. Here, 31, 32 ,. ． ． 3n is a scan flip-flop having the circuit configuration shown in FIG.

With respect to the clock signal input to the clock input terminal 312, the scan control signal is input to the scan signal input terminal 311 in the first half period. At this time, the scan flip-flops 31, 3
2 ,. ． ． 3n data output SOUT is data input S
Since IN is output as it is, the scan control signal input to the scan signal input terminal 312 is transmitted through the scan signal transmission lines 321, 322, and 32n to the scan flip-flops 31, 32 ,. ． ． It is transmitted to 3n.

If the scan control signal is the logical value "0", the circuit of FIG. 3 is in the normal operation mode and the scan flip-flops 31, 32 ,. ． ． 3n have normal data input lines 331, 332 ,. ． ． Normal data from 33n is captured at the beginning of the next cycle.

Therefore, during the normal operation, a signal having the logical value "0" is always applied to the scan control signal input terminal 311 as the scan control signal. On the other hand, in the scan mode, the scan control signal applied to the scan control signal input terminal is changed to a signal in which the first half of the clock is always a logical value "1" and the second half of the clock has a value according to the test data as described above.

When the scan control signal has the logical value "1" in the first half of the clock, the circuit of FIG. 3 is in the scan mode and the scan flip-flops 31, 32 ,. ． ． Three
The data input of n is the scan signal transmission lines 321 and 32.
2 ,. ． ． 32n. Therefore, the scan flip-flops 31, 32 ,. ． ． 3n constitutes a shift register, and scan signal input terminal 31 in the latter half cycle.
The scan data input to 1 is shift input.

As described above, the semiconductor integrated circuit according to the present embodiment has the above-described circuit configuration, so that the scan signal can be scanned without special control signal lines or control signal terminals for controlling the scan path. It is possible to divide the control signal and the scan data into the first half period and the second half period of the clock signal and transmit them to each scan flip-flop using a common signal line and signal terminal.

[0028]

As described above, according to the present invention, the scan control signal for switching between the normal operation and the scan mode and the scan data are transmitted in the first half period and the second half period by using the scan data input line in the conventional scan path circuit. Since we configured a scan path that can be transmitted separately
As compared with the conventional circuit having the scan path, the signal terminal and the signal line for scan control can be omitted, and the circuit area of the semiconductor integrated circuit can be reduced.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a flip-flop showing an embodiment of the present invention in which operation mode switching and scan data input can be performed by the same signal terminal and signal line.

FIG. 2 is a waveform diagram for explaining the operation of the circuit of FIG.

FIG. 3 is a circuit diagram showing an example in which a scan path is configured using the scan flip-flop of FIG.

FIG. 4 is a circuit diagram showing an example of a conventional scan flip-flop.

5 is a circuit diagram showing an example of a conventional scan path configured using the circuit shown in FIG.

[Explanation of symbols]

11, 13 Flip-flop 12, 15 Selector 14 Inverter 110 Clock signal input line 111 Normal data input line 112 Scan signal input line 113 Normal data output line 114 Scan signal output line 115 Data input line of flip-flop 11 116 Control signal of selector 12 Line 117 Data output line 31 to 3n of flip-flop 11 Scan flip-flop 311 implementing the present invention Scan signal input terminal 312 Clock input terminal 321 to 32n Scan signal transmission line 331 to 33n Normal data input line 341 to 34n Normal data output line 411 scan control line 51-5n conventional scan flip-flop 511 scan control terminal 521-52n scan data transmission line

Claims (1)

[Claims] 1. A semiconductor integrated circuit having a scan test mode in which a plurality of flip-flops arranged in the semiconductor integrated circuit are connected in series and predetermined test data is stored in the flip-flop. The scan signal transmission line connected to the flip-flop, the scan signal input terminal connected to the scan signal transmission line, the scan signal transmission line and the normal data input line from another circuit block are connected to the scan signal transmission line. A selection circuit for selecting one of the scan signal transmission line and the normal data input line as input data of the flip-flop according to a scan control signal input to the signal transmission line; and connected to the scan signal transmission line, Scan input from the scan signal input pin in the first half cycle in synchronization with the clock The control signal and outputs to the scan signal transfer line, a semiconductor integrated circuit, characterized in that it is provided an output circuit for outputting the output data of the flip-flop in the scan signal transmission line in the second half period.