JP2927095B2 - Test circuit for semiconductor integrated circuits - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test circuit for a semiconductor integrated circuit, and more particularly to a test circuit for a semiconductor integrated circuit in which digital and analog are mixed.

[0002]

2. Description of the Related Art As a conventional test circuit for a semiconductor integrated circuit, there is a test circuit for a semiconductor integrated circuit in which digital and analog are mixed as shown in FIG. The output end of the input buffer 3 is in the digital section 5, the digital output terminal 2 is in the output end of the output buffer 4, the input end of the output buffer 4 is in the digital section 5, the analog terminal 7 is in the analog section 6, and the digital section 5 is Each is directly connected to the analog section 6.

[0003]

However, in the above-described conventional test circuit for a semiconductor integrated circuit, since a digital section and an analog section are directly connected, a test for a semiconductor integrated circuit in which digital and analog are mixed is performed. However, there is a problem that extremely difficulties arise. That is, when testing the digital section, the signal line from the digital section to the analog section and the signal line from the analog section to the digital section cannot be directly tested, and the digital section cannot be tested indirectly from the movement of the analog section. You have to judge the quality of the product. When testing the analog section, the operation of the analog section is determined by the signal line going from the digital section to the analog section.
It is necessary to operate the digital part even though it is a test of the analog part. As described above, the conventional test circuit for a semiconductor integrated circuit has problems that the semiconductor integrated circuit cannot be directly tested and the test becomes complicated.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and it is an object of the present invention to directly and easily test digital and analog sections in a semiconductor integrated circuit in which digital and analog sections coexist. It is an object of the present invention to provide a test circuit for a semiconductor integrated circuit that can perform the above.

[0005]

SUMMARY OF THE INVENTION A test circuit for a semiconductor integrated circuit according to the present invention is a semiconductor integrated circuit having a digital part and an analog part mixed in a digital input terminal and a first input terminal.
A digital output terminal, a second digital output terminal, and an output
Select signal input terminal and analog test mode input terminal
And a digital test mode input terminal, and the digital input
An input buffer connected to the input terminal;
A first output buffer connected to the
Second output buffer connected to two digital output terminals
If, one input end connected to the signal line of the signal towards the analog section from the digital portion other input terminal is input from being coupled to said input buffer for inputting a digital signal the analog test mode input signal a first data selector controlled by, the being one input terminal is connected to a signal line of the signal toward the first output buffer from the digital section and the other input terminal an output terminal of the first data selector Connected and input from the output selection signal input terminal
A second data selector controlled by the applied signal ;
Is is one input end connected to a signal line of the signal towards the digital portion from the analog portion and the other input terminal is connected to any analog terminal or the digital test mode input terminal
The third data selector and, one input end connected to the signal line of the signal towards the second output buffer from the digital portion other input terminal said third data controlled by et input signal A fourth data selector connected to an output terminal of the selector and controlled by a signal input from the analog test mode input terminal .

[0006]

In the test circuit for a semiconductor integrated circuit according to the present invention, the first and fourth data selectors are controlled by an analog test mode signal during an analog test in a semiconductor integrated circuit in which a digital section and an analog section are mixed. In addition, data can be arbitrarily applied to the analog unit without being affected by a digital signal input from the digital input terminal and a signal input from an input terminal other than the digital input terminal and the state of the digital unit. As a result, the test of only the analog section can be directly and easily performed. Further, at the time of the digital test, the second and third data selectors are controlled by the digital test mode signal, so that the test of the digital section can be executed without being affected by the analog section and other signals. Therefore, the test circuit of the semiconductor integrated circuit according to the present invention can directly and easily test the digital section and the analog section individually.

[0007]

Next, an embodiment of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a block diagram showing a test circuit of a semiconductor integrated circuit according to a first embodiment of the present invention. In addition,
1, the same components as those of the test circuit of the conventional semiconductor integrated circuit shown in FIG. 3 are denoted by the same reference numerals as those shown in FIG.

As shown in FIG. 1, the digital input terminal 1 is connected to the input terminal of the input buffer 3, and the output terminal of the input buffer 3 is connected to the digital unit 5 and the B input terminal of the data selector 16. The digital section 5 is connected to the A input terminal of the data selector 16 via the signal line 8. The output terminal of the data selector 16 is connected to the analog section 6 and the data selector 14.
Is connected to the B input terminal. A of data selector 14
The input terminal is connected to the digital unit 5 via the signal line 11, and the output terminal of the data selector 14 is connected to the input terminal of the output buffer 4. The output terminal of the output buffer 4 is connected to the digital output terminal 2. The A input terminal of the data selector 15 is connected to the digital section 5 via the signal line 10 and the data selector 1
4 is connected to the input terminal of the output buffer 13. The output terminal of the output buffer 13 is a digital output terminal 12
It is connected to the. The analog terminal 7 is connected to the analog section 6. The A input terminal of the data selector 17 is connected to the analog unit 6 via the signal line 9, the B input terminal of the data selector 17 is connected to the analog terminal 21, and the output terminal of the data selector 17 is connected to the digital unit 5 and the B input terminals of the data selector 15. It is connected to the. The analog test mode input terminal 18 is at the switching end of the data selector 15 and the switching end of the data selector 16, the digital test mode input terminal 19 is at the switching end of the data selector 17, and the output selection input terminal 20 is at the switching end of the data selector 14. It is connected.

Next, the operation of the test circuit of the semiconductor integrated circuit according to the first embodiment configured as described above will be described. The data selectors 14, 15, 16, and 17 output data of the A input terminal when a high level signal is applied to the switching terminal, and output data of the B input terminal when a low level signal is applied to the switching terminal. Output data.

The signal input from the digital input terminal 1 is applied to the digital section 5 and the B input terminal of the data selector 16 via the input buffer 3. A signal from the digital unit 5 to the analog unit 6 is applied to the A input terminal of the data selector 16 via the signal line 8. Therefore, when a High level signal is applied to the analog test mode input terminal 18, a signal from the digital section 5 to the analog section 6 is normally applied to the analog section 6 via the data selector 16. On the other hand, when a low level signal is applied to the analog test mode input terminal 18, the signal input from the digital input terminal 1 is applied to the analog section 6 via the data selector 16.

Therefore, the signal input from the digital input terminal 1 can be arbitrarily transmitted to the analog unit 6 without being affected by the signals input from digital input terminals other than the digital input terminal 1 and the state of the digital unit 5. , The test of the analog section 6 can be easily performed.

When a High level signal is applied to the output selection input terminal 20, the data applied to the A input terminal is output in the data selector 14, so that the data normally goes from the digital 5 to the digital output terminal 2. The signal is output to the digital output terminal 2 via the signal line 11, the data selector 14, and the output buffer 4. On the other hand, when a low level signal is applied to the output selection input terminal 20, the data applied to the B input terminal is output from the data selector 14, so that the output signal of the data selector 16 is applied to the data selector 14 and the output buffer. 4 to the digital output terminal 2. Output selection input terminal 2
When a low level signal is applied to 0 and a high level signal is applied to the analog test mode input terminal 18,
A signal from the digital section to the analog section is output to the digital output terminal 2 via the signal line 8, the data selector 16, the data selector 14, and the output buffer 4, and the digital section 5 which cannot be normally tested from the outside to the analog section 6 Can be tested on the signal line 8 leading to.

When a low level signal is applied to the output selection input terminal 20 and a low level signal is also applied to the analog test mode input terminal 18, the signal applied to the digital input terminal 1 is applied to the input buffer 3, data selector 16, the data is output to the digital output terminal 2 via the data selector 14 and the output buffer 4. Therefore, the threshold voltage of the input buffer 3 can be measured by the output buffer 4, and the state of the output buffer 4 can be set by the input buffer 3 without being affected by the state of the digital section 5. Can be done.

Hi is applied to the digital test mode input terminal 19.
When the gh level signal is applied, the data applied to the A input terminal is output from the data selector 17, so that the signal from the analog section 6 to the digital section 5 is output from the data selector 17 via the signal line 9. The output is applied to the digital unit 5. When a Low level signal is applied to the digital test mode input terminal 19, a signal applied to an arbitrary analog terminal 21 is output from the data selector 17. Therefore, when a low level signal is applied to the digital test mode input terminal 19, an arbitrary signal can be applied from the analog terminal to the digital unit 5 instead of applying a signal from the analog unit 6 to the digital unit 5. The test pattern used in the test of No. 5 can be similarly used for the signal line 9 of the signal from the analog unit 6 to the digital unit 5.

Hi is applied to the analog test mode input terminal 18.
When the gh level signal is applied, the data selector 15 outputs the data applied to the A input terminal.
2 is output to the digital output terminal 12 via the signal line 10, the data selector 15, and the output buffer 13. On the other hand, Lo is input to the analog test mode input terminal 18.
When the w-level signal is applied, the data selector 15 outputs the data applied to the B input terminal, so that the output signal of the data selector 17 is output to the digital output terminal 1 via the data selector 15 and the output buffer 13.
2 is output. When a low-level signal is applied to the analog test mode input terminal 18 and a high-level signal is applied to the digital test mode input terminal 19, the signal from the analog section 6 to the digital section 5 is sent to the signal line 9 and the data selector 17. Are output to the digital output terminal 12 via the data selector 15 and the output buffer 13. Therefore, the signal line 9 of the signal from the analog section 6 to the digital section 5 can be directly tested without passing through the digital section 5.

In the first embodiment, the digital section 5
A case has been described in which one signal line 8 for a signal going from the analog section 6 to the analog section 6 and one signal line 9 for a signal going from the analog section 6 to the digital section 5 are provided. Also, by providing data selectors corresponding to the number of the signal lines, the same effect as in the first embodiment can be obtained.

FIG. 2 is a block diagram showing a test circuit of a semiconductor integrated circuit according to a second embodiment of the present invention. Book second
In the test circuit of the semiconductor integrated circuit according to the third embodiment, the analog test mode input terminal 18 is connected to the switching terminal of the data selector 14 and the input terminal of the inverter 23 in the configuration different from the first embodiment shown in FIG. , Inverter 2
3 is connected to one input terminal of the two-input NAND 22.
The other input terminal of the input NAND 22 is a portion connected to the digital test mode input terminal 19 and the output of the two-input NAND 22 is connected to the switching terminals of the data selectors 15 and 16.

Next, the operation of the test circuit of the semiconductor integrated circuit according to the second embodiment configured as described above will be described. When a low-level signal is applied to the analog test mode input terminal 18, a high-level signal is forcibly applied to the switching ends of the data selectors 15 and 16 by the two-input NAND 22 and the inverter 23. The output signal of the data selector 14 can be switched by a signal input from the analog test mode input terminal 18.

Thus, the test circuit for the semiconductor integrated circuit according to the second embodiment has the same function as the test circuit for the semiconductor integrated circuit according to the first embodiment without using the output selection input terminal. Therefore, the circuit can be simplified, and the test of the semiconductor integrated circuit can be further facilitated.

[0021]

As described above, according to the test circuit for a semiconductor integrated circuit of the present invention, the digital circuit can be configured by using a data selector in a semiconductor integrated circuit in which digital and analog are mixed. And the testing of the analog sections individually directly and easily.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a test circuit of a semiconductor integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a test circuit of a semiconductor integrated circuit according to a second embodiment of the present invention.

FIG. 3 is a block diagram showing an example of a conventional test circuit for a semiconductor integrated circuit.

[Explanation of symbols]

 Reference Signs List 1; digital input terminal 2; digital output terminal 3; input buffer 4, 13; output buffer 5; digital unit 6; analog unit 7, 21; analog terminal 14, 15, 16, 17; data selector 18; Terminal 19: Digital test mode input terminal 20; Output selection input terminal

Claims (1)

(57) [Claims] In a semiconductor integrated circuit in which a digital part and an analog part are mixed, a digital input terminal and a first digital
Output terminal, second digital output terminal, output selection
Signal input terminal, analog test mode input terminal,
Digital test mode input terminal and the digital input terminal
An input buffer connected to the first digital output
A first output buffer connected to a terminal;
A second output buffer connected to the digital output terminal, connected to said input buffer having one input terminal and the other input terminal is connected to a signal line of the signal towards the analog section from the digital section to input a digital signal a first data selector which is controlled by a signal inputted from the analog test mode input terminal is, the one input terminal is connected to a signal line of the signal toward the first output buffer from the digital portion other input The terminal is connected to the output terminal of the first data selector and is input from the output selection signal input terminal.
A second data selector controlled by the signal, one of said input terminals connected to the other input terminal to the signal line of the signal towards the digital portion from the analog part is connected to any analog terminal the digital test mode input Input from terminal
A third data selector controlled by the applied signal;
Is that which one input terminal is connected to a signal line of the signal towards the second output buffer from the digital section and the other input terminal connected to an output terminal of said third data selector input from the analog test mode input terminal And a fourth data selector controlled by the signal.