JPS6120424A - Logical circuit - Google Patents

Abstract

PURPOSE:To process a signal at a high speed by generating in advance by a logical operation the first output signal in case when it is assumed that logic of a binary signal is ''0'', and the second output signal in case when it is assumed that logic of the binary signal is ''1'', with respect to the binary signal which is delayed and inputted. CONSTITUTION:In logical circuits 1a, 1b, in the circuit 1a, a signal of logic ''0'' and logic ''L'' is connected to a terminal 4a corresponding to a terminal 4 to which a signal C is inputted by a circuit 1, and in the circuit 1b, a signal of logic ''1'' and logic ''H'' is connected to a terminal 4b. Accordingly, after a processing time tau from a time point t0 when signals A and B have arrived, output signals of terminals 5a, 5b are settled and inputted to a selector 6. Therefore, at the time point t1 when the signal C has arrived, one of the signals from the terminal 5a or 5b is outputted as an output signal D, therefore, the time between the input time point t0 of the signals A, B and the output time point t1 of the signal D goes to t1-t0, and it is shortened comparing with the conventional (t1-t0)+tau.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to logic circuits, and particularly to increasing the speed of signal processing thereof.

[Prior art]

FIG. 1 is a block diagram showing a conventional logic circuit, in which (1) is a logic circuit, 12! , i3+ , f4+
tri is a signal input terminal, +51 Vi signal output terminal, A', B, and C are human binary signals, respectively, and Ll is an output signal.

In the case of the configuration shown in Fig. 1, one of the input binary signals, for example, signal C, may be input later than the other signals A and B. In such a case, signal C may be input later than the other signals A and B. Later, processing is performed in the logic circuit Yamauchi and the signal is output, so the input point I of the signal C is t-to1 at the human input point of the signals A and B.
t1, and the processing time of the logic circuit (1) is τ, the output time t2 of the signal is tl +τ, and the input time t of the signals A and H. There was a drawback that the time was delayed by 10τ from (11-1o).

[Summary of the invention]

This invention was made in order to eliminate the drawbacks of the conventional ones as described above, and in this invention, for a binary signal that is input with a delay, the logic of the binary signal is "0". A first output signal when it is assumed that the logic of the binary signal is "1" and a second output signal when it is assumed that the logic of the binary signal is "1" are generated in advance by a logical operation, and the output signal is generated after a delay. When the input binary signal arrives, the first
The output signal or the second output signal is selected.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 is a block diagram showing an embodiment of the present invention, in which (1a) is the first logic circuit, (lb) is the second logic circuit, (2a), (2b), (3a), (3bL(4
a).

(4b) are signal input terminals, (5a) and (5b) respectively.
tri is a signal output terminal, (6) is a selector, (
7) is a control signal terminal of the selector; 6). Also A, B.

Ct-t As in the case of FIG. 1, each input binary signal, D is an output signal, and among the input binary signals, the signal CH selector 161 U)? The Ii control signal is input to the input terminal (7), and the output signal is output from the DVi selector (61).

Logic circuit (la), (lb) V'i Logic circuit in Fig. 1 (
The circuit (1a) has the same structure and operates in the same way as the circuit (1), but the terminal (4a) corresponding to the terminal (41) to which the signal C is input in the circuit (1:) has a logic "0" (logic "L"). The signal is connected, and in the circuit (1b), the terminal (4b) has Vi logic “1”.
” (logic “H”) signal is connected.

Therefore, after a processing time τ from the time to when the signals A and B arrive, the output signals of the terminals (5a) and (5b) are set and input to the selector 16).

Therefore, at the time t1 when the signal C arrives, the terminal (5a
) or the signal from terminal (5b) is output as the output signal.
The time between t1 and the output time t1 of the signal is 1. -1o
This is shorter than the conventional (11-18)+τ.

In the above embodiment, a logic one-channel VC with three human power and one output was explained, but it may have multiple inputs and multiple outputs, and as long as it is a digital circuit in which the output logic is uniquely determined based on the input logic. , the present invention can be applied even to non-logic circuits. Therefore, the term "logic circuit" as used in this specification includes all digital circuits in which the logic of the output is uniquely determined by the logic of the input.

〔Effect of the invention〕

As described above, according to the present invention, a delay of m force caused by a delayed input can be absorbed into a delay corresponding to the output selection, thereby speeding up the processing.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional circuit, and FIG. 2 is a block diagram showing an embodiment of the present invention. (1a)...Ol arithmetic circuit, (1b)...Second arithmetic circuit, (za), (2b), (:ta), (3b)
, (4a), (4b) ---signal input terminals, (
5a), (5b)...signal output terminal, (6) respectively
···selector.

Claims (1)

[Claims] In a logic circuit that generates an output signal by processing three or more input binary signals by a predetermined logical operation, a specific binary signal selected from the plurality of input binary signals. a first logic circuit that generates a first output signal by processing a logic "0" signal in place of the logic "0" signal and the other input binary signal by the above-mentioned predetermined logic operation; a second logic circuit that processes the logic "1" signal and the other input binary signal by the predetermined logic operation to generate a second output signal; 1. A logic circuit comprising means for selectively outputting either the first output signal or the second output signal.