JPS6136947A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6136947A JPS6136947A JP15980584A JP15980584A JPS6136947A JP S6136947 A JPS6136947 A JP S6136947A JP 15980584 A JP15980584 A JP 15980584A JP 15980584 A JP15980584 A JP 15980584A JP S6136947 A JPS6136947 A JP S6136947A
- Authority
- JP
- Japan
- Prior art keywords
- output
- semiconductor device
- chip
- terminals
- output circuits
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 238000010586 diagram Methods 0.000 description 7
- 238000006243 chemical reaction Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 3
- 101000905241 Mus musculus Heart- and neural crest derivatives-expressed protein 1 Proteins 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は半導体装置に関し、特に出力レベルの変換につ
いての半導体装置間の接続方法を改善したところの半導
体装置に関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which a connection method between semiconductor devices for output level conversion is improved.
（従来の技術）
従来、この種の半導体装置は電子計算機、交換機及び端
末機等で多く使用され各装置間の汎用性を高めている。(Prior Art) Conventionally, this type of semiconductor device has been widely used in electronic computers, switchboards, terminals, etc., increasing the versatility of each device.
第２図及び第３図はそれぞれ従来の半導体装置の一例の
要部を示すチップパターン図及びその半導体装置使用の
接続方法の一例を示すブロック図である。FIGS. 2 and 3 are a chip pattern diagram showing a main part of an example of a conventional semiconductor device, and a block diagram showing an example of a connection method using the semiconductor device, respectively.
第２図は１種類の出力レベルを有する半導体装置の例で
あり、チップ１１上に設けられた、出力回路１２．出力
端子１３及び出力回路と出力端子間１３を接続する配線
１４を含むことから構成されている。FIG. 2 shows an example of a semiconductor device having one type of output level, in which output circuits 12 . It is configured to include an output terminal 13 and a wiring 14 connecting the output circuit and the output terminal 13.
第３図は第２図で説明した半導体装置を他のレベルを有
する半導体装置に接続する例であり、第２図の半導体装
置２１及びレベル変換回路２２から構成されている。FIG. 3 shows an example in which the semiconductor device explained in FIG. 2 is connected to a semiconductor device having another level, and is composed of the semiconductor device 21 and the level conversion circuit 22 shown in FIG.
半導体装置２１の入力端子２３に入力された信号レベル
は、レベル変換回路２２により変換され出力端子２４は
他のレベルの半導体装置と接続可能である。しかし、半
導体装置２１とレベル変換回路２２間の接続、いわゆる
端子間接続により速度の遅れが加算され、高性能化には
反し、又、接続端子が多くなるので高信頼性を実現する
ことは難しいという問題があった。The signal level input to the input terminal 23 of the semiconductor device 21 is converted by the level conversion circuit 22, and the output terminal 24 can be connected to a semiconductor device of another level. However, the connection between the semiconductor device 21 and the level conversion circuit 22, so-called terminal-to-terminal connection, adds a speed delay, which is counter to high performance, and it is difficult to achieve high reliability because the number of connection terminals increases. There was a problem.
（発明の目的）
本発明の目的は、上記問題点を解消することＫより、高
性能・高信頼性を有する半導体装置を提供することにあ
る。(Objective of the Invention) An object of the present invention is to provide a semiconductor device having high performance and high reliability, rather than solving the above-mentioned problems.
（発明の構成）
本発明の半導体装置は、同一チップ上に形成された。２
種類以上のレベルの異なる出方回路と、該出力回路のう
ちのいずれか選択された出力回路を出力端子に接続する
配線とを有することがら構成される。(Structure of the Invention) The semiconductor device of the present invention is formed on the same chip. 2
It is configured to include output circuits of different levels than those of different types, and wiring that connects any selected one of the output circuits to an output terminal.
（実施例）
以下、本発明の実施例について図面を参照して説明する
。(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.
第１図は本発明の一実施例の要部を示すチップパターン
図である。FIG. 1 is a chip pattern diagram showing a main part of an embodiment of the present invention.
本実施例は、同一チ、グ３１上に形成された、２種類の
レベルの異なる出力回路Ａ３２ａ及び出力回路Ｂ５２ｂ
とこれらの出力回路のうちの選択された出力回路Ａ３２
ａを出力端子３３に接続する配線３４とを有することか
ら構成される。In this embodiment, an output circuit A32a and an output circuit B52b of two different levels are formed on the same chip 31.
and the output circuit A32 selected from these output circuits.
a and a wiring 34 connecting the output terminal 33 to the output terminal 33.
すなわち、本実施例は、同一チップ３１上にあらかじめ
配置しである出力レベルの異なる出力回路Ａ３２ａ及び
出力回路Ｂ５２ｂ （ここで、出力レベルｔｉＴＴＬレ
ベル、 ＥＣＬレベル又ｕＬｃＭＬレベル等制限は無い
さを接続する入力形式により配線系マスクによシ、所望
の出力レベルを得るように出力回路を選択して配線する
ことにより得られる。That is, in this embodiment, an output circuit A 32a and an output circuit B 52b having different output levels, which are arranged in advance on the same chip 31, are connected. This can be achieved by selecting and wiring an output circuit to obtain a desired output level based on a wiring system mask depending on the input format.
よって、端子間接続が無くなることにより高性能及び高
信頼性な半導体装置を得ることができる。Therefore, since there is no connection between terminals, a high performance and highly reliable semiconductor device can be obtained.
（発明の効果）
本発明は以上説明したように、同一チップ上に２種類以
上のレベルの異なる回路金膜け、必要に応じて選択でき
るように構成することにより高性能・高信頼性の半導体
装置を得るととがで色る。(Effects of the Invention) As explained above, the present invention provides a semiconductor with high performance and high reliability by configuring two or more types of circuit gold films of different levels on the same chip so that they can be selected as necessary. When you get the device, it becomes colored with spikes.
第１図は本発明の一実施例の要部を示すチップパターン
図、第２図は従来の半導体装置の一例の要部を示すチッ
プパターン図、第３図は第２図の半導体装置使用の接続
方法の一例を示すプロ、り図である。
３１・・・・・・チップ、３２＆・・・・・・出力回路
Ａ、３２ｂ・・・・・・出力回路Ｂ１３３・・・・・・
出力端子、３４・・・・・・配線。
事 １ 図FIG. 1 is a chip pattern diagram showing the main part of an embodiment of the present invention, FIG. 2 is a chip pattern diagram showing the main part of an example of a conventional semiconductor device, and FIG. 3 is a chip pattern diagram showing the main part of an example of a conventional semiconductor device. It is a professional diagram showing an example of a connection method. 31... Chip, 32 &... Output circuit A, 32b... Output circuit B133...
Output terminal, 34... Wiring. Thing 1 Figure
Claims (1)
なる出力回路と、該出力回路のうちのいずれか選択され
た出力回路を出力端子に接続する配線とを有することを
特徴とする半導体装置。What is claimed is: 1. A semiconductor device comprising: two or more types of output circuits of different levels formed on the same chip; and wiring for connecting any selected one of the output circuits to an output terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15980584A JPS6136947A (en) | 1984-07-30 | 1984-07-30 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15980584A JPS6136947A (en) | 1984-07-30 | 1984-07-30 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6136947A true JPS6136947A (en) | 1986-02-21 |
Family
ID=15701641
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15980584A Pending JPS6136947A (en) | 1984-07-30 | 1984-07-30 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6136947A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1992002052A1 (en) * | 1990-07-19 | 1992-02-06 | Seiko Epson Corporation | Master slice semiconductor integrated circuit |
-
1984
- 1984-07-30 JP JP15980584A patent/JPS6136947A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1992002052A1 (en) * | 1990-07-19 | 1992-02-06 | Seiko Epson Corporation | Master slice semiconductor integrated circuit |
| US5352939A (en) * | 1990-07-19 | 1994-10-04 | Seiko Epson Corporation | Master slice semiconductor integrated circuit with output drive current control |
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