JPH0297049A - Package device for integrated circuit use - Google Patents

Package device for integrated circuit use

Info

Publication number
JPH0297049A
JPH0297049A JP63249351A JP24935188A JPH0297049A JP H0297049 A JPH0297049 A JP H0297049A JP 63249351 A JP63249351 A JP 63249351A JP 24935188 A JP24935188 A JP 24935188A JP H0297049 A JPH0297049 A JP H0297049A
Authority
JP
Japan
Prior art keywords
integrated circuit
conductor
package device
lead pin
circuit use
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63249351A
Other languages
Japanese (ja)
Inventor
Keizo Oda
織田　敬三
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP63249351A priority Critical patent/JPH0297049A/en
Publication of JPH0297049A publication Critical patent/JPH0297049A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To make it possible to increase the number of the input/output signal pins of an IC without enlarging a package device for integrated circuit use by a method wherein the lead pin parts of the device are formed into a laminated structure of a conductor part, an insulator part and a conductor part and the conductor parts for two kinds of lead pins are arranged in the same direction. CONSTITUTION:Lead pin parts of a package device for integrated circuit use are formed into a laminated structure of a conductor part 3, an insulator part 2 and a conductor part 1 and the conductor parts 3 and 1 for 2 kinds of lead pins are arranged in the same direction. Thereby, as two different signals can be allocated to a place to correspond to one conventional lead pin, the number of input/output signal pins of an IC can be increased without enlarging the package device for integrated circuit use.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は集積回路用パッケージ装置に関するものであ
る。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] This invention relates to a packaging device for integrated circuits.

〔従来の技術〕[Conventional technology]

第３図は従来の集積回路用パッケージ装置の断面図で、
図において、（１）はリードピン、（４）はＩＣチップ
、（５）はプラスチックモールド樹脂部である。Figure 3 is a cross-sectional view of a conventional integrated circuit packaging device.
In the figure, (1) is a lead pin, (4) is an IC chip, and (5) is a plastic mold resin part.

従来の集積回路用パッケージ装置は入力・出力信号とリ
ードピン（１）とが１対１の対応になっていたため、入
力・出力信号ピンの数だけリードピン（１）が必要であ
る。In conventional integrated circuit packaging devices, input/output signals and lead pins (1) have a one-to-one correspondence, and therefore, as many lead pins (1) as there are input/output signal pins are required.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

従来の集積回路用パッケージ装置は以上のように構成さ
れていたので、ＩＣの入力・出力信号が増加するに伴い
集積回路用パッケージ装置のリードピンの数も増加し、
そのため集積回路用パッケージ装置が大きくなるという
問題点があった。Conventional integrated circuit packaging devices have been configured as described above, and as the number of IC input/output signals increases, the number of lead pins in integrated circuit packaging devices also increases.
Therefore, there is a problem in that the integrated circuit packaging device becomes large.

この発明は上記のような問題点を解消するためになされ
たもので、集積回路用パッケージ装置を大きくすること
な（ＩＣの入力・出力信号ピンの数を増やすことができ
る集積回路用パッケージ装置を得ることを目的とする。This invention was made in order to solve the above-mentioned problems, and it is possible to create an integrated circuit packaging device that can increase the number of input/output signal pins of an IC without increasing the size of the integrated circuit packaging device. The purpose is to obtain.

〔課題を解決するための手段〕[Means to solve the problem]

この発明に係る集積回路用パッケージ装置はリードピン
部を導体部、絶縁体部、導体部の積層構造とし、２種の
リードピン用導体部を同一方向に配置したものである。In the integrated circuit package device according to the present invention, the lead pin portion has a laminated structure of a conductor portion, an insulator portion, and a conductor portion, and two types of lead pin conductor portions are arranged in the same direction.

〔作用〕[Effect]

この発明のリードピン部の積層構造は２種のリードピン
用導体部を同一方向に配置することにより、従来１本の
り−ドピンに相等する個所に異なる２つの信号が割り当
てられ、集積回路用パッケージ装置を大きくすることな
（ＩＣの入力・出力信号のピン数を増やすことが可能と
なる。The laminated structure of the lead pin portion of the present invention has two types of lead pin conductor portions arranged in the same direction, so that two different signals are assigned to the location equivalent to a single wired pin, which makes it possible to improve the integrated circuit package device. (It is possible to increase the number of pins for input/output signals of the IC without increasing the size.)

〔実施例〕〔Example〕

以下、この発明の一実施例を図について説明する。第１
図において、（１）は第１のリードピン用導体部、（３
）は第２のリードピン用導体部、（２）は導体部（１）
と（３）を電気的に分離するための絶縁体部、（４）は
ＩＣチップ、（５）はプラスチックモールド樹脂部であ
る。An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, (1) is the first lead pin conductor part, (3
) is the second lead pin conductor part, (2) is the conductor part (1)
(4) is an IC chip, and (5) is a plastic molded resin part.

次に動作について説明する。第１図に示すように、２種
のり−ドピン用導体部（１１（３１と絶縁体部（２）の
積層構造とし、リードピン用導体部（１）と（３）を同
一方向に配置したことによって、従来１本のリードピン
（１）に相等する個所に異なる２つの信号を割り当てる
ことができる。Next, the operation will be explained. As shown in Figure 1, it has a laminated structure of two types of lead pin conductor parts (11 (31) and an insulator part (2), and the lead pin conductor parts (1) and (3) are arranged in the same direction. Accordingly, two different signals can be assigned to a location equivalent to one conventional lead pin (1).

また−上記実施例ではデュアルインラインパッケージ装
置の場合について説明したが、フラットパッケージ装置
であってもよく上記実施例と同様の効果を奏する。Further, in the above embodiment, a case of a dual in-line package device has been described, but a flat package device may also be used and the same effects as in the above embodiment can be obtained.

〔発明の効果〕〔Effect of the invention〕

以上のようにこの発明によれば、リードピン部を導体絶
縁体、導体の積層構造とし２種のリードピン用導体部を
同一方向に配置したので、従来１本のリードピンに相等
する個所に異なる２つの信号を割り当てることができ、
集積回路用パッケージ装置を大きくすることなく、ＩＣ
の入力・出力信号ピンの数を増やすことができる。As described above, according to the present invention, the lead pin part has a laminated structure of a conductor insulator and a conductor, and two types of lead pin conductor parts are arranged in the same direction. signals can be assigned,
IC without increasing the size of integrated circuit packaging equipment
The number of input/output signal pins can be increased.

【図面の簡単な説明】[Brief explanation of drawings]

第１図はこの発明の一実施例による集積回路用パッケー
ジ装置の断面図、第２図は第１図の側面図、第３図は従
来の集積回路用パッケージ装置の断面図、第４図は第３
図の側面図である。 図において、ｆｉｌ　１３１はリードピン用導体部、（
２）は絶縁体部、（４）はＩＣチップ、（５）はプラス
チックモールド樹脂部を示す。 なあ、図中、同一符号は同一、または相当部分を示す。FIG. 1 is a sectional view of an integrated circuit packaging device according to an embodiment of the present invention, FIG. 2 is a side view of FIG. 1, FIG. 3 is a sectional view of a conventional integrated circuit packaging device, and FIG. 4 is a sectional view of a conventional integrated circuit packaging device. Third
FIG. In the figure, fil 131 is the lead pin conductor part, (
2) shows an insulator part, (4) shows an IC chip, and (5) shows a plastic mold resin part. In the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

【特許請求の範囲】[Claims] 　集積回路用パッケージ装置のリードピン部分を導体部
、絶縁体部、導体部の積層構造とし、２種のリードピン
用導体部を同一方向に配置したことを特徴とする集積回
路用パッケージ装置。A package device for an integrated circuit, characterized in that a lead pin portion of the package device for an integrated circuit has a laminated structure of a conductor portion, an insulator portion, and a conductor portion, and two types of conductor portions for lead pins are arranged in the same direction.
JP63249351A 1988-10-03 1988-10-03 Package device for integrated circuit use Pending JPH0297049A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63249351A JPH0297049A (en) 1988-10-03 1988-10-03 Package device for integrated circuit use

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63249351A JPH0297049A (en) 1988-10-03 1988-10-03 Package device for integrated circuit use

Publications (1)

Publication Number Publication Date
JPH0297049A true JPH0297049A (en) 1990-04-09

Family

ID=17191734

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63249351A Pending JPH0297049A (en) 1988-10-03 1988-10-03 Package device for integrated circuit use

Country Status (1)

Country Link
JP (1) JPH0297049A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5592019A (en) * 1994-04-19 1997-01-07 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and module
DE102016119078A1 (en) * 2016-10-07 2018-04-12 Infineon Technologies Ag Carrier, circuit, semiconductor device package

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5592019A (en) * 1994-04-19 1997-01-07 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and module
DE102016119078A1 (en) * 2016-10-07 2018-04-12 Infineon Technologies Ag Carrier, circuit, semiconductor device package
DE102016119078B4 (en) * 2016-10-07 2020-07-09 Infineon Technologies Ag Carrier, circuit, semiconductor device package

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