JPS61117858A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS61117858A JPS61117858A JP59238387A JP23838784A JPS61117858A JP S61117858 A JPS61117858 A JP S61117858A JP 59238387 A JP59238387 A JP 59238387A JP 23838784 A JP23838784 A JP 23838784A JP S61117858 A JPS61117858 A JP S61117858A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- semiconductor chips
- tab
- semiconductor device
- same
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49575—Assemblies of semiconductor devices on lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔技術分野〕
本発明は半導体装置に関し、特に実装面積を縮小させる
際に用いて好適な半導体集積回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a semiconductor device, and particularly to a semiconductor integrated circuit suitable for use in reducing the mounting area.
電子機器の技術的動向の一つに小形・軽量化があり、こ
れにともなって半導体集積回路（以下−おいてＩＣとい
う）も高集積度化の傾向にある。One of the technological trends in electronic equipment is miniaturization and weight reduction, and with this trend, semiconductor integrated circuits (hereinafter referred to as ICs) are also becoming more highly integrated.
一方、回路技術の発達により、電子機器内におい工アナ
ログ回路による信号処理とディジタル信号による信号処
理が行われることがある。このような場合、アナログ回
路とディジタル回路とを共存させたＩＣがあれば回路設
計上におい℃極めて便利である。また、プリント基板へ
の実装についても、アナログ用ＩＣとディジタル用ＩＣ
とを個別に実装する必要がなく、実装面積の縮小を計る
と同時に上記技術的動向をも満足することができる。On the other hand, with the development of circuit technology, signal processing using analog circuits and digital signals may be performed in electronic devices. In such a case, it would be extremely convenient in circuit design if there was an IC that had both an analog circuit and a digital circuit. In addition, regarding mounting on printed circuit boards, analog IC and digital IC
There is no need to separately mount these elements, and it is possible to reduce the mounting area and at the same time satisfy the above-mentioned technological trends.
なお、特公昭４５−１１３７号公報には、同一パッケー
ジ内において同一平面に複数の半導体チップを設けた半
導体装置が開示され℃いる。また、［日経エレクトロニ
クスＪ（１９８３年１２月１９日号、日経マグロウヒル
社発行、ｐ８２〜ｐ８５）には、ＩＣを薄く樹脂封止す
るパッケージが記載されている。Note that Japanese Patent Publication No. 45-1137 discloses a semiconductor device in which a plurality of semiconductor chips are provided on the same plane within the same package. Furthermore, [Nikkei Electronics J (December 19, 1983 issue, published by Nikkei McGraw-Hill, p. 82 to p. 85) describes a package in which an IC is thinly sealed with resin.
本発明の目的は、ＩＣの実装面積な大幅に縮小し得ると
ともに、実質的に高集積度となる半導体装置を提供する
ことにある。An object of the present invention is to provide a semiconductor device that can significantly reduce the mounting area of an IC and has a substantially high degree of integration.
本発明σ上記ならびにその他の目的と新規な特徴は５本
明細書の記述および添付図面から明らかになるであろう
。The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.
本願において開示される発明の概要を簡単に述べれば、
下記のとおりである。A brief summary of the invention disclosed in this application is as follows:
It is as follows.
すなわち、同一パッケージ内圧アナログ用半導体チップ
、或いはディジタル用半導体チップの如何を問わず積層
した状態に設けることＫより、１個のＩＣ面積で複数の
ＩＣの働きを得るとともに。In other words, since semiconductor chips for internal pressure analog or digital semiconductor chips are provided in a stacked state in the same package, the functions of a plurality of ICs can be obtained with one IC area.
ＩＣ実装時の実装面積を縮小させる、という本発明の目
的を達成するものである。This achieves the object of the present invention, which is to reduce the mounting area during IC mounting.
〔実施例−１〕
次に、第１図〜第３図を参照して本発明を適用した半導
体装置の第１実施例を述べる。なお、以下に述べる各実
施例１１半導体装雪としてＩＣが用いられ工いる。[Embodiment 1] Next, a first embodiment of a semiconductor device to which the present invention is applied will be described with reference to FIGS. 1 to 3. Note that an IC is used as the semiconductor device in each of the embodiments 11 described below.
第１図に示すように、上段のタブ１上には第１の半導体
チップ２が設けられ、半導体チップ２に形成された端子
（図示せず）と各インナーリード３．４の先端とは、Ａ
Ｕ線５，６等によりワイヤボンディングされている。な
お、各インナーリード３，４の他端は、バクケージ７の
外部に突出しアウターリード８，９となる。As shown in FIG. 1, a first semiconductor chip 2 is provided on the upper tab 1, and a terminal (not shown) formed on the semiconductor chip 2 and the tip of each inner lead 3.4 are connected to each other. A
Wire bonding is performed using U wires 5, 6, etc. The other end of each inner lead 3, 4 protrudes to the outside of the back cage 7 and becomes outer leads 8, 9.
一方、下段のタブ１１上には第２の半導体チップ１２が
設けられ、半導体チップ１２に形成された端子（図示せ
ず）と各インナーリード１３゜１４０先端とは、Ａｕ線
（又は、ＡＪ線）１５゜１６等によりワイヤボンディン
グされている。なお、各インナーリード１３，１４の他
端はパッケージ７の外部に突出し、アウターリード１８
゜１９となる。On the other hand, a second semiconductor chip 12 is provided on the lower tab 11, and a terminal (not shown) formed on the semiconductor chip 12 and the tip of each inner lead 13°140 are connected to an Au wire (or an AJ wire). )15°16 etc. are wire bonded. The other end of each inner lead 13, 14 protrudes outside the package 7, and the outer lead 18
It becomes ゜19.
ここで注目すべきは、同一パッケージ７内罠第１及び第
２の半導体チップ２，１２が積層されて設けられること
により、２倍の集積度となるばかりでな（第２図に示す
如く１個のＩＣとして実装し得ることである。この場合
、上記半導体チップ１．１１は同一機能のものでよく、
或いはディジタル用ＩＣとアナログ用ＩＣの如く異なっ
た機能のものでもよい。また、一方が変調回路で他方が
増幅回路であり工もよい。従りて、実装時にはＩＣ１個
分の面積を占有するのみで、ＩＣ２個分あるいは３個分
もの機能を得ることができ、実質的に実装面積を大幅に
縮小できることになる。What should be noted here is that by providing the first and second semiconductor chips 2 and 12 in the same package 7 in a stacked manner, the degree of integration is not only doubled (as shown in FIG. In this case, the semiconductor chips 1.11 may have the same function,
Alternatively, they may have different functions, such as a digital IC and an analog IC. In addition, one side is a modulation circuit and the other is an amplifier circuit, making it easy to construct. Therefore, at the time of mounting, it is possible to obtain the functions of two or three ICs by only occupying the area of one IC, thereby substantially reducing the mounting area.
また、アクタ−リード８，１８０間とアウターリード９
，１９との間は、実装時の配線パターンを考慮して所望
の幅Ｗに設定し得るので、プリント基板（図示せず）の
設計も容易に行ない得る。Also, between the actor leads 8 and 180 and the outer lead 9
, 19 can be set to a desired width W in consideration of the wiring pattern at the time of mounting, so that the printed circuit board (not shown) can be easily designed.
なお、＠３図は上記ＩＣをモールドする際の一例を示す
ものであり、上金型３１、スペース用金型３２、下金型
３３で形成されたスペースＳ内にワイヤボンディングさ
れた第１及び第２の半導体チップ２、工２を設け、注入
孔３１ａ、３３ａから例えばレジン（図示せず）等を注
入してパッケージ７を形成する。このように、上下から
レジン等のモールド材を注入することにより、短時間に
モールド作業を行うことができると同時Ｋ、いわゆるワ
イヤ流れによる不所望の事故を低減することもできる。Note that Figure @3 shows an example of molding the above IC, and shows the first and second wires bonded in the space S formed by the upper mold 31, the space mold 32, and the lower mold 33. A second semiconductor chip 2 and a process 2 are provided, and a package 7 is formed by injecting, for example, resin (not shown) through injection holes 31a and 33a. In this way, by injecting molding material such as resin from above and below, the molding work can be carried out in a short time, and at the same time, it is also possible to reduce undesirable accidents caused by so-called wire drift.
〔実施例−２〕 次Ｋ、第４図を参照して本発明の第２実施例を述べる。[Example-2] Next, a second embodiment of the present invention will be described with reference to FIG.
なお、上記第１実施例と同一部分には同一の符号を付し
、説明の重複をさけるものとする。Note that the same parts as in the first embodiment are given the same reference numerals to avoid duplication of explanation.
第４図はＩＣの低面図を示すものであり、アウターリー
ド８，１８とアウターリード９．１９とは所望の幅Ｗに
形成されると同時に及互に突出するように形成されてい
る。この場合、プリント基板上に形成される配線パター
ンの設計が極めて容易になる。FIG. 4 shows a bottom view of the IC, and the outer leads 8, 18 and outer leads 9, 19 are formed to have a desired width W and are formed to protrude from each other. In this case, designing the wiring pattern formed on the printed circuit board becomes extremely easy.
〔実施例−３〕 次に、第５図を参照して本発明の第３実施例を述べる。[Example-3] Next, a third embodiment of the present invention will be described with reference to FIG.
なお、上記各実施例と同一部分には同一の符号を付し、
説明の重複をさけるものとする。Note that the same parts as in each of the above embodiments are given the same reference numerals.
Duplicate explanations shall be avoided.
第５図に示すように、タブ１はタブ下げリード（図示せ
ず）によってインナーリード３，４よりは下方に位置し
、その上部に第１の半導体テップ２が設けられている。As shown in FIG. 5, the tab 1 is located below the inner leads 3 and 4 by a tab lower lead (not shown), and the first semiconductor tip 2 is provided above.
これに対し、第２の半導体チップ１２はタブ１１の下側
に設けられ、第１及び第２の半導体チップ２，１２０間
に２枚のタブ１．１１が介在している。On the other hand, the second semiconductor chip 12 is provided below the tab 11, and two tabs 1.11 are interposed between the first and second semiconductor chips 2,120.
上記構成によれば、各半導体チップ２，１２から発生し
た熱がタブ１ 、１１によって遮断され、互いの熱によ
る悪影響を低減することができる。According to the above configuration, the heat generated from each of the semiconductor chips 2 and 12 is blocked by the tabs 1 and 11, and the adverse effects of heat on each other can be reduced.
また、上記各実施例に比較し、ＩＣ全体の高さを小にす
ることができる。Furthermore, the height of the entire IC can be made smaller than in each of the above embodiments.
〔実施例−４〕 次に、第６図を参照して本発明の第４実施例を述べる。[Example-4] Next, a fourth embodiment of the present invention will be described with reference to FIG.
なお、上記各実施例と同一部分には同一の符号を付し、
説明の重複をさけるものとする。Note that the same parts as in each of the above embodiments are given the same reference numerals.
Duplicate explanations shall be avoided.
第６図に示すよう罠、半導体チップ１は上記第３実施例
と同様にタブ下げリードによって保持されている。そし
て、インナーリード３，１３の間にはスペーサ２１が設
けられ、インナーリード４゜１４０間にはスペーサ２２
が設けられて、それぞれ一定の間隔を保持するように構
成されている。As shown in FIG. 6, the semiconductor chip 1 is held by tab lower leads as in the third embodiment. A spacer 21 is provided between the inner leads 3 and 13, and a spacer 22 is provided between the inner leads 4 and 140.
are provided and are configured to maintain a constant interval between them.
一方、第２の半導体チップ３１はインナーリード１３，
１４の下側にワイヤーを用いることなく直付けになされ
ている。On the other hand, the second semiconductor chip 31 has inner leads 13,
It is directly attached to the lower side of 14 without using wires.
本実施例に示す構成によれば、ＩＣ全体の高さを更に小
にすることができ、第１及び第２の半導体チップ２，３
１間の距離を大にして、熱による悪影響を低減すること
ができる。According to the configuration shown in this embodiment, the height of the entire IC can be further reduced, and the first and second semiconductor chips 2, 3
1 can be increased to reduce the adverse effects of heat.
ｉｌ＋ 同一パッケージ内に複数の半導体チップを積
層して設けることにより、多機能のＩＣを得ることがで
きる。il+ By stacking and providing a plurality of semiconductor chips in the same package, a multifunctional IC can be obtained.
＋２１ 上記１１７により、Ｉ（’の実装面積を実質
的に縮小する、という効果が得られる。+21 The above 117 has the effect of substantially reducing the mounting area of I('.
以上本発明者によっ℃なされた発明を実施例にもとづき
具体的に説明したが、本発明は上記実施例に限定される
ものではなく、その要旨を逸脱しない範囲で種々変更可
能であることはいうまでもない。Although the invention made by the present inventor has been specifically explained based on Examples above, the present invention is not limited to the above Examples, and it is understood that various changes can be made without departing from the gist of the invention. Needless to say.
例えば、上記半導体チップ２，１２は２個に限定されず
、３個あるいは４個の半導体チップを積層してもよい。For example, the number of semiconductor chips 2 and 12 is not limited to two, and three or four semiconductor chips may be stacked.
また、第１及び第２の半導体チップ２，１２１、アナロ
グ用、ディジタル用の何れであってもよい。Furthermore, the first and second semiconductor chips 2, 121 may be either analog or digital.
また、単一のタブの上側面と下側面とに半導体チップを
設けてもよい。Further, semiconductor chips may be provided on the upper and lower sides of a single tab.
以上の説明では、主として本発明者によってなされた発
明をその背景となった利用分野である半導体集積回路に
ついて説明したが、それに限定されるものではない。In the above description, the invention made by the present inventor has mainly been described with respect to semiconductor integrated circuits, which is the field of application behind the invention, but the invention is not limited thereto.
例えば、ハイブレット’ＩＣに利用することができる。For example, it can be used for Hybret' IC.
第１図は本発明の第１実施例を示す半導体装置の要部の
断面図を示し、
第２図は上記半導体装置の外形図を示し、第３図は上記
半導体装置の製造方法を示し。
第４図は本発明の第２実施例を示す半導体装置の低面図
を示し、
第５図は本発明の第３実施例を示す半導体装置の要部の
断面図を示し、
第６図は本発明の第４実施例を示す半導体装置の要部の
断面図を示す。
１．１１・・・タブ、２，１２．３１・・・半導体チッ
プ、３，４，１３．１４・・・インナーリード、８゜９
．１８．１９・・・アクタ−リード、５，６，１５゜１
６・・・ボンディングワイヤー、７・・・パッケージ、
２１．２２・・・スペーサ。
第 １ 図
第 ２ 図
／Ｙ ？
第 ３ 図
第 ４ 図
Ｗ γ Ｗ
第 ５ 図
第 ６ 図FIG. 1 shows a sectional view of essential parts of a semiconductor device showing a first embodiment of the present invention, FIG. 2 shows an external view of the semiconductor device, and FIG. 3 shows a method of manufacturing the semiconductor device. FIG. 4 shows a bottom view of a semiconductor device showing a second embodiment of the present invention, FIG. 5 shows a sectional view of main parts of a semiconductor device showing a third embodiment of the invention, and FIG. A sectional view of a main part of a semiconductor device showing a fourth embodiment of the present invention is shown. 1.11...Tab, 2,12.31...Semiconductor chip, 3,4,13.14...Inner lead, 8°9
．． 18.19...Actor lead, 5, 6, 15°1
6... Bonding wire, 7... Package,
21.22...Spacer. Figure 1 Figure 2/Y? Figure 3 Figure 4 W γ W Figure 5 Figure 6
Claims (1)
設けたことを特徴とする半導体装置。1. A semiconductor device characterized by having a plurality of semiconductor chips stacked in the same package.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59238387A JPS61117858A (en) | 1984-11-14 | 1984-11-14 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59238387A JPS61117858A (en) | 1984-11-14 | 1984-11-14 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61117858A true JPS61117858A (en) | 1986-06-05 |
Family
ID=17029435
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59238387A Pending JPS61117858A (en) | 1984-11-14 | 1984-11-14 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61117858A (en) |
Cited By (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6340846B1 (en) | 2000-12-06 | 2002-01-22 | Amkor Technology, Inc. | Making semiconductor packages with stacked dies and reinforced wire bonds |
| US6395578B1 (en) | 1999-05-20 | 2002-05-28 | Amkor Technology, Inc. | Semiconductor package and method for fabricating the same |
| US6452278B1 (en) | 2000-06-30 | 2002-09-17 | Amkor Technology, Inc. | Low profile package for plural semiconductor dies |
| US6472758B1 (en) | 2000-07-20 | 2002-10-29 | Amkor Technology, Inc. | Semiconductor package including stacked semiconductor dies and bond wires |
| US6531784B1 (en) | 2000-06-02 | 2003-03-11 | Amkor Technology, Inc. | Semiconductor package with spacer strips |
| US6552416B1 (en) | 2000-09-08 | 2003-04-22 | Amkor Technology, Inc. | Multiple die lead frame package with enhanced die-to-die interconnect routing using internal lead trace wiring |
| US6555917B1 (en) | 2001-10-09 | 2003-04-29 | Amkor Technology, Inc. | Semiconductor package having stacked semiconductor chips and method of making the same |
| US6577013B1 (en) | 2000-09-05 | 2003-06-10 | Amkor Technology, Inc. | Chip size semiconductor packages with stacked dies |
| US6642610B2 (en) | 1999-12-20 | 2003-11-04 | Amkor Technology, Inc. | Wire bonding method and semiconductor package manufactured using the same |
| US6737750B1 (en) | 2001-12-07 | 2004-05-18 | Amkor Technology, Inc. | Structures for improving heat dissipation in stacked semiconductor packages |
| US6798049B1 (en) | 1999-08-24 | 2004-09-28 | Amkor Technology Inc. | Semiconductor package and method for fabricating the same |
| US6879047B1 (en) | 2003-02-19 | 2005-04-12 | Amkor Technology, Inc. | Stacking structure for semiconductor devices using a folded over flexible substrate and method therefor |
| US6946323B1 (en) | 2001-11-02 | 2005-09-20 | Amkor Technology, Inc. | Semiconductor package having one or more die stacked on a prepackaged device and method therefor |
| US7154171B1 (en) | 2002-02-22 | 2006-12-26 | Amkor Technology, Inc. | Stacking structure for semiconductor devices using a folded over flexible substrate and method therefor |
| US7485490B2 (en) | 2001-03-09 | 2009-02-03 | Amkor Technology, Inc. | Method of forming a stacked semiconductor package |
| US8017440B2 (en) | 2009-10-07 | 2011-09-13 | Renesas Electronics Corporation | Manufacturing method for semiconductor devices |
| US20160379933A1 (en) * | 2007-02-21 | 2016-12-29 | Amkor Technology, Inc. | Semiconductor package in package |
-
1984
- 1984-11-14 JP JP59238387A patent/JPS61117858A/en active Pending
Cited By (23)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6395578B1 (en) | 1999-05-20 | 2002-05-28 | Amkor Technology, Inc. | Semiconductor package and method for fabricating the same |
| US6762078B2 (en) | 1999-05-20 | 2004-07-13 | Amkor Technology, Inc. | Semiconductor package having semiconductor chip within central aperture of substrate |
| US6798049B1 (en) | 1999-08-24 | 2004-09-28 | Amkor Technology Inc. | Semiconductor package and method for fabricating the same |
| US6642610B2 (en) | 1999-12-20 | 2003-11-04 | Amkor Technology, Inc. | Wire bonding method and semiconductor package manufactured using the same |
| US6803254B2 (en) | 1999-12-20 | 2004-10-12 | Amkor Technology, Inc. | Wire bonding method for a semiconductor package |
| US6531784B1 (en) | 2000-06-02 | 2003-03-11 | Amkor Technology, Inc. | Semiconductor package with spacer strips |
| US6452278B1 (en) | 2000-06-30 | 2002-09-17 | Amkor Technology, Inc. | Low profile package for plural semiconductor dies |
| US6650019B2 (en) | 2000-07-20 | 2003-11-18 | Amkor Technology, Inc. | Method of making a semiconductor package including stacked semiconductor dies |
| US6472758B1 (en) | 2000-07-20 | 2002-10-29 | Amkor Technology, Inc. | Semiconductor package including stacked semiconductor dies and bond wires |
| US6577013B1 (en) | 2000-09-05 | 2003-06-10 | Amkor Technology, Inc. | Chip size semiconductor packages with stacked dies |
| US6552416B1 (en) | 2000-09-08 | 2003-04-22 | Amkor Technology, Inc. | Multiple die lead frame package with enhanced die-to-die interconnect routing using internal lead trace wiring |
| US6340846B1 (en) | 2000-12-06 | 2002-01-22 | Amkor Technology, Inc. | Making semiconductor packages with stacked dies and reinforced wire bonds |
| US7485490B2 (en) | 2001-03-09 | 2009-02-03 | Amkor Technology, Inc. | Method of forming a stacked semiconductor package |
| US6555917B1 (en) | 2001-10-09 | 2003-04-29 | Amkor Technology, Inc. | Semiconductor package having stacked semiconductor chips and method of making the same |
| US6946323B1 (en) | 2001-11-02 | 2005-09-20 | Amkor Technology, Inc. | Semiconductor package having one or more die stacked on a prepackaged device and method therefor |
| US6737750B1 (en) | 2001-12-07 | 2004-05-18 | Amkor Technology, Inc. | Structures for improving heat dissipation in stacked semiconductor packages |
| US6919631B1 (en) | 2001-12-07 | 2005-07-19 | Amkor Technology, Inc. | Structures for improving heat dissipation in stacked semiconductor packages |
| US7154171B1 (en) | 2002-02-22 | 2006-12-26 | Amkor Technology, Inc. | Stacking structure for semiconductor devices using a folded over flexible substrate and method therefor |
| US6879047B1 (en) | 2003-02-19 | 2005-04-12 | Amkor Technology, Inc. | Stacking structure for semiconductor devices using a folded over flexible substrate and method therefor |
| US20160379933A1 (en) * | 2007-02-21 | 2016-12-29 | Amkor Technology, Inc. | Semiconductor package in package |
| US9768124B2 (en) | 2007-02-21 | 2017-09-19 | Amkor Technology, Inc. | Semiconductor package in package |
| US8017440B2 (en) | 2009-10-07 | 2011-09-13 | Renesas Electronics Corporation | Manufacturing method for semiconductor devices |
| US8569111B2 (en) | 2009-10-07 | 2013-10-29 | Renesas Electronics Corporation | Manufacturing method for semiconductor devices |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS61117858A (en) | Semiconductor device | |
| US6667560B2 (en) | Board on chip ball grid array | |
| JPH04307943A (en) | Semiconductor device | |
| US6340839B1 (en) | Hybrid integrated circuit | |
| US6791166B1 (en) | Stackable lead frame package using exposed internal lead traces | |
| JP2560805B2 (en) | Semiconductor device | |
| JP2001156251A (en) | Semiconductor device | |
| JPS5818949A (en) | Semiconductor device | |
| US5719748A (en) | Semiconductor package with a bridge for chip area connection | |
| JP2681427B2 (en) | Semiconductor device | |
| JPS6020524A (en) | Semiconductor integrated circuit device | |
| JP2541532B2 (en) | Semiconductor module | |
| JPS617657A (en) | Package for multi-chip | |
| JP2913858B2 (en) | Hybrid integrated circuit | |
| JPH06268012A (en) | Semiconductor integrated circuit | |
| KR940008644Y1 (en) | System board level package | |
| JPH027459A (en) | Semiconductor package | |
| JPH0697666A (en) | Electronic device | |
| JP2555991B2 (en) | package | |
| KR100210712B1 (en) | Semiconductor integrated circuit device using semiconductor chip having electrode pad array for stability wire bonding | |
| JPS6081852A (en) | Semiconductor device | |
| JPH081943B2 (en) | Semiconductor integrated circuit package | |
| JPH05211279A (en) | Hybrid integrated circuit | |
| JPH0974167A (en) | Semiconductor module | |
| JPS62169463A (en) | Semiconductor device |