JPS60234335A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS60234335A JPS60234335A JP59091213A JP9121384A JPS60234335A JP S60234335 A JPS60234335 A JP S60234335A JP 59091213 A JP59091213 A JP 59091213A JP 9121384 A JP9121384 A JP 9121384A JP S60234335 A JPS60234335 A JP S60234335A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- bonding
- inner lead
- lead frame
- pad
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/49105—Connecting at different heights
- H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/494—Connecting portions
- H01L2224/4943—Connecting portions the connecting portions being staggered
- H01L2224/49433—Connecting portions the connecting portions being staggered outside the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術的背景〕
本発明は、チップとインナリードとの接続に改良を加え
た半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Background of the Invention] The present invention relates to a semiconductor device in which the connection between a chip and an inner lead is improved.
従来、半導体装置としては、第１図（ａ）、（ｂ）に示
すものが知られている。なお、同図（ａ）は平面図、同
図（’ ｂ ）は同図（ａ）を部分的に拡大した平面図
である。2. Description of the Related Art Conventionally, semiconductor devices shown in FIGS. 1(a) and 1(b) are known. It should be noted that FIG. 5A is a plan view, and FIG. 1B is a partially enlarged plan view of FIG.
図中の１は、縁部に複数の第１のポンディングパッド２
・・・を設けたチップである。このチップ１の周囲には
、先端が第２のポンディングパッド３・・・になってい
るインナーリード４・・・が設けられている。なお、こ
れらインナーリードフレーム４・・・を総称してインナ
ーリードフレームど呼ぶ。前記第１のポンディングパッ
ド２・・・と第２のポンディングパッド３・・・は、夫
々ボンディングワイヤ５・・・によって接続されている
。1 in the figure indicates a plurality of first bonding pads 2 on the edge.
It is a chip equipped with... Around this chip 1, inner leads 4 are provided, the tips of which become second bonding pads 3. Note that these inner lead frames 4 are collectively referred to as an inner lead frame. The first bonding pads 2 and the second bonding pads 3 are connected by bonding wires 5, respectively.
しかるに、現在、ＩＣの集積化が進み、多ビン化の傾向
が強くなっており、多ビン化に対応したＩＣパッケージ
が必要とされている。しかしながら、従来技術で多ビン
化に対応すると、多ピンに見合うインナーリードの数を
確保するために、パッケージが大型化したり、インナー
リードの線幅が微細化したり、あるいは第２図に示す如
くインナーリードが階段状に設【プられたすする。この
ため、種々の問題が生じる。即ち、パッケージの大型化
は、ＩＣの特徴である小形化の意ＭＥ失わせたり、入出
力ピンの静電容量を増加させてダイナミックの電気特性
を劣化させたり、あるいはホンディングワイヤ５を長く
させてワイヤ間の短絡を生じさせたりする。前記インナ
ルリードの線幅の微細化は、マシーンの精度を要求し、
マシーン自体のコスト高をもたらす。However, as ICs are currently becoming more integrated, there is a growing trend toward multi-bin packaging, and there is a need for IC packages that can accommodate multiple bins. However, when conventional technology is used to support the increase in the number of bins, in order to secure the number of inner leads commensurate with the number of pins, the package becomes larger, the line width of the inner leads becomes finer, or as shown in Fig. The reeds are set up in a stepped manner. This causes various problems. In other words, increasing the size of the package may cause the user to lose the desire for miniaturization, which is a characteristic of ICs, may increase the capacitance of input/output pins and deteriorate the dynamic electrical characteristics, or may cause the wire 5 to become longer. This can cause short circuits between wires. The miniaturization of the line width of the inner lead requires high precision of the machine,
This results in higher costs for the machine itself.
本発明は、上記事情に鑑みてなされたもので、ボンディ
ングワイヤの長さを従来と比べて短くしてワイヤ間の短
絡を防止するとともに、低コスト、高集積度で静電容量
の小さい半導体装置を提供することを目的とするもので
ある。The present invention has been made in view of the above circumstances, and it is possible to prevent a short circuit between the wires by making the length of the bonding wire shorter than that of the conventional one, and to provide a low-cost, highly integrated semiconductor device with small capacitance. The purpose is to provide the following.
本発明は、少なくともチップとインナーリードフレーム
の夫々のコーナ一部間に中継用パッドを設け、第１のポ
ンディングパッド、中継用パッド間、及び中継用パッド
、第２のボンティングパット間に夫々ホンディングヮイ
Ｖを設【ノることによって、前述した種々の目的を達成
しようとしたものである。The present invention provides a relay pad between at least a portion of each corner of the chip and the inner lead frame, and provides bonding pads between the first bonding pad and the relay pad, and between the relay pad and the second bonding pad, respectively. By setting up the Honda Motor Vehicle V, we attempted to achieve the various objectives mentioned above.
（発明の実施例） 以下、本発明の一実施例を第３図を参照して説明する。(Example of the invention) An embodiment of the present invention will be described below with reference to FIG.
図中の１１は、チップである。このチップ１１の縁部に
は、複数の第１のポンディングパッド１２・・・が設け
られている。これらパッド１２・・・の間隔は、チップ
１１の台片の中央部からコーナーに近ずくにつれて広く
なっている。前記デツプ１１の周囲には、該チップ１１
から離間して複数の第２のポンディングパッド１３・・
・を有したインナーリード１４・・・が設けられている
。なお、これらインナーリード１４・・・を総称してイ
ンナーリードフレームと呼ぶ。前記パッド１３・・・は
、夫々デツプ１１の台片に対して２列で千鳥状に配列さ
れている。前記デツプ１１とインナーリードフレームの
夫々のコーナ一部間には、中継用バンド１５・・・が設
けられている。前記第１のホンディングバッド１２・・
・と中継用バラｌ’ １５・・・間、及びこれら中幇用
パッド１５・・・と第２のホンディングバット１３間に
は、夫々複数のボンディングワイヤ１６・・・がコーナ
一部から順に設けられている。また、チップ１１の台片
の中央部及びその付近の第１のポンディングパッド１２
・・・とこれに近い第２のポンディングパッド１３・・
・は、別のボンディングワイヤ１７・・・によって直接
接続されている。11 in the figure is a chip. A plurality of first bonding pads 12 . . . are provided on the edge of this chip 11 . The spacing between these pads 12 . . . becomes wider from the center of the base piece of the chip 11 toward the corners. Around the depth 11, the chip 11
A plurality of second pounding pads 13 are spaced apart from each other.
An inner lead 14 having an inner lead 14 is provided. Note that these inner leads 14 are collectively referred to as an inner lead frame. The pads 13 are arranged in two rows in a staggered manner with respect to the base of the depth 11, respectively. A relay band 15 is provided between the depth 11 and a portion of each corner of the inner lead frame. Said first homing pad 12...
A plurality of bonding wires 16 are connected between the intermediate pads 15 and the second bonding butts 13, starting from a part of the corner. It is provided. In addition, the first bonding pad 12 is located in the center of the base piece of the chip 11 and in the vicinity thereof.
...and a second pounding pad 13 similar to this...
* are directly connected by another bonding wire 17...
しかして、本発明によれば、チップ１１とインナーリー
ドフレームの夫々のコーナ一部間に中継用バッド１５・
・・を設け、この中継用バッド１５・・・を介してチッ
プ１１のコーナ一部の第１のボンデ−（ングバット１２
・・・と、インナーリードフレームのコーナ一部の第２
のボンディングバラ１−１３・・・の接続を行なうため
、従来と比べ、コーナ一部でのホンディングワイヤ１６
・・・の長さを短かくてきる。従って、従来パッケージ
の大型化に起因して生じたボンディングワイヤ間の短絡
を回避できる。According to the present invention, the relay pad 15 is provided between the chip 11 and a portion of each corner of the inner lead frame.
... is provided, and a first bonding butt 12 is connected to a part of the corner of the chip 11 via the relay pad 15...
...and the second part of the corner of the inner lead frame.
In order to connect the bonding roses 1-13..., the bonding wires 16 at some corners are
... shorten the length. Therefore, it is possible to avoid short circuits between bonding wires that have conventionally occurred due to the increase in size of packages.
また、上記と同様な理由により、パッケージの大型化を
せずに、多ビン化に対応したＩＣパッケージが得られる
ため、素子を高集積度化できるとともに、静電容量が増
加してダイナミックな電気的特性が劣化することもなく
、しかもコストを低減できる。更に、インナーリード１
４・・・の第２のボンディングフレーム１３・・・が２
列に配列されているため、第２のボンディングバット１
３・・・の数を一層増やすことかでき、素子の高集積化
を促進できる。In addition, for the same reason as above, an IC package that can accommodate multiple bins can be obtained without increasing the size of the package, allowing for higher integration of elements and increasing capacitance to enable dynamic electrical There is no deterioration in physical characteristics, and costs can be reduced. Furthermore, inner lead 1
The second bonding frame 13 of 4... is 2
Because they are arranged in rows, the second bonding butt 1
3... can be further increased, and higher integration of elements can be promoted.
なお、本発明に係る半導体装置は、上記実施例のものに
限らず、例えば、第４図に示す如く、中継用パッド２１
・・・をチップ１１の各月に対して夫々平行に設けた構
造のものでもよい。なお、図中の２２・・・はボンディ
ングワイヤを示″ｇ。ここで、第２のボンディングフレ
ームの間隔を、インナーリードフレームの各月の中央部
からコーナーに近ずくにつれて広くすれば、ボンディン
グ間の短絡を一層防止できる。It should be noted that the semiconductor device according to the present invention is not limited to the above-mentioned embodiment, and for example, as shown in FIG.
... may be provided in parallel to each month of the chip 11. Note that 22... in the figure indicates bonding wires. Here, if the interval between the second bonding frames is increased from the center of each month of the inner lead frame to the corner, the bonding distance can be increased. Short circuits can be further prevented.
また、上記実施例では、中継用パッドの形状を略一様に
形成したが、これに限らず、例えば図示しないが、ボン
ディングワイヤと接続する部分のみ太くなった形状のも
のでもよい。このような形状にすることにより、中継用
パッドとこのパッド下のグランド用又は信号用配線との
容量を小さくすることができる。Further, in the above embodiment, the shape of the relay pad is formed to be substantially uniform, but the shape is not limited to this, and, for example, although not shown, it may have a shape in which only the portion connected to the bonding wire is thickened. By adopting such a shape, the capacitance between the relay pad and the ground or signal wiring under the pad can be reduced.
以上詳述した如く本発明によれば、同一チップに対して
多ビン化が実現でき、ボンティングワイヤ間の短絡を防
止するとともに、コスト低減、高集積度化でき−かつ静
電容量の小さい半導体装置を提供できる。As detailed above, according to the present invention, multiple bins can be realized on the same chip, short circuits between bonding wires can be prevented, costs can be reduced, high integration can be achieved, and semiconductors with small capacitance can be realized. equipment can be provided.
第１図（ａ）は従来の半導体装置の平面図、同図（ｂ）
は同図（ａ）の部分拡大平面図、第２図は従来の他の半
導体装置の概略斜視図、第３図は本発明の一実施例に係
る半導体装置の平面図、第４図は本発明の他の実施例に
係る半導体装置の平面図である。
１１・・・チップ、１２．１３・・・ポンディングパッ
ド、１４・・・インナーリードフレーム、１５．２１・
・・中継用パラ１−１１６．１７．２２・・・ボンディ
ングワイヤ。
出願人代理人 弁理士 鈴江武彦
第１図（ａ）
（ｂ）
第２図
第３図FIG. 1(a) is a plan view of a conventional semiconductor device, and FIG. 1(b) is a plan view of a conventional semiconductor device.
2 is a schematic perspective view of another conventional semiconductor device, FIG. 3 is a plan view of a semiconductor device according to an embodiment of the present invention, and FIG. 4 is a partially enlarged plan view of FIG. FIG. 7 is a plan view of a semiconductor device according to another embodiment of the invention. 11... Chip, 12.13... Bonding pad, 14... Inner lead frame, 15.21.
...Relay Para 1-116.17.22...Bonding wire. Applicant's agent Patent attorney Takehiko Suzue Figure 1 (a) (b) Figure 2 Figure 3
Claims (4)
、このチップの周囲に配設された複数の第２のポンディ
ングパッドを有したインナーリードフレームと、少なく
とも前記チップとインナーリードフレームの夫々のコー
ナ一部間に設けられた中継用パッドと、第１のポンディ
ングパッド、中継用パッド間、及び中継用パッド、第２
のポンティングパッド間に夫々設けられたボンディング
ワイヤとを具備することを特徴とする半導体装置。(1) A chip provided with a plurality of first bonding pads, an inner lead frame having a plurality of second bonding pads arranged around the chip, and at least each of the chip and the inner lead frame. Between the relay pad provided in one corner, the first bonding pad, the relay pad, and the relay pad, the second
and bonding wires provided between the respective ponting pads of the semiconductor device.
パッドを複列化したことを特徴とする特許請求の範囲第
１項記載の半導体装置。(2) The semiconductor device according to claim 1, characterized in that the second bonding pads of the inner lead frame are arranged in double rows.
チップの多片の中央部からコーナーに近ずくにつれて広
くすることを特徴とする特許請求の範囲第１項記載の半
導体装置。(3), the distance between the first bonding pads of the chip is
2. The semiconductor device according to claim 1, wherein the width increases from the center of each of the multiple pieces of the chip toward the corners.
パッドの間隔を、インナーリードフレームの多片の中央
部からコーナーに近ずくにつれて広くすることを特徴と
する特許請求の範囲第１項記載の半導体装置。(4) The semiconductor according to claim 1, wherein the distance between the second bonding pads of the inner lead frame is increased from the center of the multiple pieces of the inner lead frame to the corners thereof. Device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59091213A JPS60234335A (en) | 1984-05-08 | 1984-05-08 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59091213A JPS60234335A (en) | 1984-05-08 | 1984-05-08 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60234335A true JPS60234335A (en) | 1985-11-21 |
Family
ID=14020140
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59091213A Pending JPS60234335A (en) | 1984-05-08 | 1984-05-08 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60234335A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63224335A (en) * | 1987-03-13 | 1988-09-19 | Sharp Corp | Semiconductor integrated circuit device |
| JPH0249133U (en) * | 1988-09-29 | 1990-04-05 | ||
| US5309016A (en) * | 1991-05-30 | 1994-05-03 | Fujitsu Limited | Semiconductor integrated circuit device having terminal members provided between semiconductor element and leads |
| WO2001020669A3 (en) * | 1999-09-16 | 2001-10-04 | Koninkl Philips Electronics Nv | Use of additional bonding finger rows to improve wire bond density |
-
1984
- 1984-05-08 JP JP59091213A patent/JPS60234335A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63224335A (en) * | 1987-03-13 | 1988-09-19 | Sharp Corp | Semiconductor integrated circuit device |
| JPH057865B2 (en) * | 1987-03-13 | 1993-01-29 | Sharp Kk | |
| JPH0249133U (en) * | 1988-09-29 | 1990-04-05 | ||
| US5309016A (en) * | 1991-05-30 | 1994-05-03 | Fujitsu Limited | Semiconductor integrated circuit device having terminal members provided between semiconductor element and leads |
| US5361970A (en) * | 1991-05-30 | 1994-11-08 | Fujitsu Limited | Method of producing a semiconductor integrated circuit device having terminal members provided between semiconductor element and leads |
| WO2001020669A3 (en) * | 1999-09-16 | 2001-10-04 | Koninkl Philips Electronics Nv | Use of additional bonding finger rows to improve wire bond density |
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