JPS63224335A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPS63224335A JPS63224335A JP62058489A JP5848987A JPS63224335A JP S63224335 A JPS63224335 A JP S63224335A JP 62058489 A JP62058489 A JP 62058489A JP 5848987 A JP5848987 A JP 5848987A JP S63224335 A JPS63224335 A JP S63224335A
- Authority
- JP
- Japan
- Prior art keywords
- pad
- lead wire
- relaying
- integrated circuit
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 9
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 claims abstract description 31
- 230000005540 biological transmission Effects 0.000 claims abstract description 7
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000010276 construction Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 239000003292 glue Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
この発明は半導体集積回路装置に関し、特に集積回路チ
ップの電極パッドとパッケージの外部端子との接続に関
するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and more particularly to connection between electrode pads of an integrated circuit chip and external terminals of a package.
〔従来の技術１
近年、Ｑａ″ＡＳ ＦＥＴ、Ｓｉバイポーラトランジス
タ等を用いたＵＨＦＨＦ帯金雑音増幅器研究開発が活発
に行なわれている。特に、複数のＦＥＴ、付随する整合
回路等を１つのチップ上に構成するいわゆるモノリシッ
ク集積回路技術は、低コスト性、高信頼性等の有利な特
徴を持つので、様々なデバイスへの応用が検討され、実
用化されている。[Conventional technology 1] In recent years, research and development of UHFHF band noise amplifiers using Qa″AS FETs, Si bipolar transistors, etc. has been actively conducted.In particular, it is difficult to integrate multiple FETs, accompanying matching circuits, etc. onto a single chip. The so-called monolithic integrated circuit technology that is constructed in this way has advantageous features such as low cost and high reliability, so its application to various devices has been studied and put into practical use.
このような従来のモノリシック集積回路においては、整
合回路等を製造段階でチップ上に構成するので、チップ
完成後に所望の回路特性が得られなかった場合には、回
路を調整することが不可能であった。そこで従来は、設
計を変更して所望の特性が得られるまで試行錯誤を繰返
す手法が多く採用されていた。In such conventional monolithic integrated circuits, matching circuits and the like are configured on the chip at the manufacturing stage, so if the desired circuit characteristics cannot be obtained after the chip is completed, it is impossible to adjust the circuit. there were. Therefore, in the past, many methods have been adopted in which the design is changed and trial and error is repeated until the desired characteristics are obtained.
［発明が解決しようとする問題点］
、上記のように試行錯誤を繰返す手法の場合、多くのチ
ップを個々に調整することになるので、コストが嵩み、
モノリシック化の長所である低コスト性に反することと
なり、モノリシック化することの意味がなくなってしま
うという問題点があった。[Problems to be solved by the invention] In the case of the trial-and-error method described above, many chips must be adjusted individually, which increases costs.
This goes against the advantage of monolithic construction, which is low cost, and there is a problem in that monolithic construction has no meaning.
そこで、この発明は上記の問題点を解決するためになさ
れたもので、チップ完成侵に整合回路を微調整すること
が可能な半導体集積回路装置を提供することを目的とす
る。SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide a semiconductor integrated circuit device in which a matching circuit can be finely adjusted as the chip is completed.
Ｅ問題点を解決するための手段］
この発明に係る半導体集積回路装置は、集積回路チップ
の電極パッドとパッケージの外部端子との間に帯状の伝
送線路からなる中継用バッドを設け、第１のリード線に
より前記電極パッドと前記中継用バッドの任意の位置と
を接続するとともに、第２のリード線により前記外部端
子と前記中継用バッドの任意の位置とを接続したもので
ある。Means for Solving Problem E] The semiconductor integrated circuit device according to the present invention provides a relay pad made of a band-shaped transmission line between the electrode pad of the integrated circuit chip and the external terminal of the package, and A lead wire connects the electrode pad to an arbitrary position on the relay pad, and a second lead wire connects the external terminal to an arbitrary position on the relay pad.
［作用］
一般に集積回路のパッケージを行なう場合には、パッケ
ージングによる寄生的回路要素の介在を極力避けるよう
に行なっている。また、集積回路の入出力の直列インダ
クタンスは回路特性に影響を与えるので、従来はこの影
響を避けるために、集積回路チップの電極パッドとパッ
ケージの外部端子とを接続するリード線の長さを極力短
くし、インダクタンスを小さくしていた。しかし、この
発明においては、この直列インダクタンスの影響を積極
的に利用し、リード線の長さを変えることを可能に構成
し、リード線の良さを変えることによって直列インダク
タンスの大きさを変え、回路の調整を行なうようにして
いる。[Operation] Generally, when packaging an integrated circuit, the intervention of parasitic circuit elements due to packaging is avoided as much as possible. In addition, since the series inductance of the input and output of an integrated circuit affects the circuit characteristics, conventionally, in order to avoid this effect, the length of the lead wire connecting the electrode pad of the integrated circuit chip and the external terminal of the package was minimized. It was made shorter and the inductance was reduced. However, in this invention, the effect of this series inductance is actively utilized, the length of the lead wire can be changed, and the size of the series inductance can be changed by changing the quality of the lead wire. We are trying to make adjustments.
すなわち、この発明に係る半導体集積回路装置において
は、中継用バッドにおける第１のリード線および第２の
リード線を接続する位置を変えることによって、リード
線の長さを調整することができ、それによって直列イン
ダクタンスの大ぎさを調整することができる。That is, in the semiconductor integrated circuit device according to the present invention, the length of the lead wire can be adjusted by changing the connecting position of the first lead wire and the second lead wire in the relay pad. The magnitude of the series inductance can be adjusted by
［実施例］ 以下、この発明の実施例を図面を用いて説明する。[Example] Embodiments of the present invention will be described below with reference to the drawings.
第１図はこの発明の一実施□例である半導体集積回路装
置の構成を示す概略図である。FIG. 1 is a schematic diagram showing the configuration of a semiconductor integrated circuit device which is an example of implementing the present invention.
図において、集積回路チップ１上の所定位置には、入力
バッド２および出力バッド３が設けられている。そして
、この集積回路チップ１の外方には、パッケージの入力
端子４および出力端子５が位置している。この発明の半
導体集積回路装置においては、入力バッド２と入力端子
４との間および出力バッド３と出力端子５との間に、そ
れぞれ帯状の中継用バッド６．７が設けられている。In the figure, an input pad 2 and an output pad 3 are provided at predetermined positions on an integrated circuit chip 1. An input terminal 4 and an output terminal 5 of the package are located outside the integrated circuit chip 1. In the semiconductor integrated circuit device of the present invention, strip-shaped relay pads 6 and 7 are provided between the input pad 2 and the input terminal 4 and between the output pad 3 and the output terminal 5, respectively.
この中継用バッド６．７は、低損失でかつ高特性インピ
ーダンスの伝送線路により形成されている。入力バッド
２と中継用バッド６とは第１のり一ドＪ０８によって接
続され、入力端子４と中継用バッド６とは第２のリード
線１０によって接続される。また、出力バッド３と中継
用バッド７とは第１のリード線９によって接続され、出
力端子５ど中継用バッド７とは第２のリード線１１によ
って接続される。This relay pad 6.7 is formed of a transmission line with low loss and high characteristic impedance. The input pad 2 and the relay pad 6 are connected by a first glue wire J08, and the input terminal 4 and the relay pad 6 are connected by a second lead wire 10. Further, the output pad 3 and the relay pad 7 are connected by a first lead wire 9, and the output terminal 5 and the relay pad 7 are connected by a second lead wire 11.
第１のリード線８．９および第２のリード線１０．１１
は中継用バッド６．７の任意の位置・に接続することが
でき、接続する位置を変えることによって、リード線の
長さを任意に調整することができる。たとえば、リード
線の長さを長くする場合には、点線で示すように接続す
る。First lead wire 8.9 and second lead wire 10.11
can be connected to any position on the relay pad 6.7, and by changing the connection position, the length of the lead wire can be adjusted as desired. For example, when increasing the length of the lead wire, connect it as shown by the dotted line.
このようにリード線長を任意に調整することができるの
で、入出力各２本のリード線により、インダクタンスの
大きさを任意に調整することができ、所望の特性が得ら
れるように整合回路の微調整を行なうことができる。Since the length of the lead wires can be adjusted arbitrarily in this way, the size of the inductance can be adjusted arbitrarily by using two lead wires for each input and output, and the matching circuit can be adjusted to obtain the desired characteristics. Fine adjustments can be made.
第２図は、この発明の他の実施例の構成を示す概略図で
ある。FIG. 2 is a schematic diagram showing the configuration of another embodiment of the invention.
図において、集積回路デツプ１上の入力バッド２とパッ
ケージの入力端子４とを接続するための中継用バッド６
は、蛇行するように形成された帯状の伝送線路からなり
、この中継用バッド６は伝送線路用低損失基板１２上に
形成されている。In the figure, a relay pad 6 is used to connect the input pad 2 on the integrated circuit deep 1 and the input terminal 4 of the package.
consists of a belt-shaped transmission line formed in a meandering manner, and this relay pad 6 is formed on a low-loss substrate 12 for the transmission line.
入力バッド２と中継用バッド６とは第１のり一ド線８に
より接続され、入力端子４と中継用バッド６とは第２の
リード１１０により接続される。The input pad 2 and the relay pad 6 are connected by a first lead wire 8, and the input terminal 4 and the relay pad 6 are connected by a second lead 110.
中継用バッド６においてこれらの第１のリード線８また
は第２のリード線１０を接続する位置ａ。A position a where these first lead wires 8 or second lead wires 10 are connected in the relay pad 6.
ｂ、ｃ、ｄ、ｅ、ｆ、ｇを変えることによって、第１の
実施例の場合と同様に、リード線長を任意に調整するこ
とができる。By changing b, c, d, e, f, and g, the lead wire length can be arbitrarily adjusted as in the first embodiment.
この実施例の場合は、リード線を接続する位置を一定さ
せることができるので、リード線長の再現性に優れてい
る。In the case of this embodiment, since the position where the lead wire is connected can be made constant, the reproducibility of the lead wire length is excellent.
なお、第２図の実施例においては、入力側しか示してい
ないが、出力側も同様にしてインダクタンスの微調整を
することができる。In the embodiment of FIG. 2, only the input side is shown, but the inductance can be finely adjusted in the same way on the output side.
［発明の効果］
以−［のようにこの発明によれば、集積回路チップの電
極パッドとパッケージの外部端子との間に中継用パッド
を設け、この中継用パッドにおいてリード線を接続する
位置を変えることによって、電極パッドと外部端子間の
リード線長を調整し、直列インダクタンスをｗ４１！す
ることができる。したがって、集積回路チップ完成後の
整合回路の微調整が可能とにｒる。[Effects of the Invention] As described above, according to the present invention, a relay pad is provided between the electrode pad of the integrated circuit chip and the external terminal of the package, and the position at which the lead wire is connected to the relay pad is determined. By changing the length of the lead wire between the electrode pad and the external terminal, the series inductance can be adjusted to w41! can do. Therefore, it is possible to finely adjust the matching circuit after the integrated circuit chip is completed.
第１図はこの発明による半導体集積回路装置の一実施例
を示す概略図、第２図は他の実施例を示す概略図である
。
図において、１は集積回路チップ、２は入力パッド、３
は出力パッド、４は入力端子、５は出力端子、６．７Ｉ
よ中継用パッド、８，９は第１のリード線、１０．１１
は第２のリード線、１２は伝送線路用低損失基板を示す
。
め １ 田
、第２ 回FIG. 1 is a schematic diagram showing one embodiment of a semiconductor integrated circuit device according to the present invention, and FIG. 2 is a schematic diagram showing another embodiment. In the figure, 1 is an integrated circuit chip, 2 is an input pad, and 3 is an integrated circuit chip.
is the output pad, 4 is the input terminal, 5 is the output terminal, 6.7I
Relay pads, 8 and 9 are first lead wires, 10.11
12 indicates a second lead wire, and 12 indicates a low-loss substrate for a transmission line. Me 1 field, 2nd episode
Claims (1)
の間に帯状の伝送線路からなる中継用パッドを設け、第
１のリード線により前記電極パッドと前記中継用パッド
の任意の位置とを接続するとともに、第２のリード線に
より前記外部端子と前記中継用パッドの任意の位置とを
接続した半導体集積回路装置。A relay pad made of a belt-shaped transmission line is provided between an electrode pad of the integrated circuit chip and an external terminal of the package, and a first lead wire connects the electrode pad to any arbitrary position of the relay pad. . A semiconductor integrated circuit device in which the external terminal and any position of the relay pad are connected by a second lead wire.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62058489A JPS63224335A (en) | 1987-03-13 | 1987-03-13 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62058489A JPS63224335A (en) | 1987-03-13 | 1987-03-13 | Semiconductor integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63224335A true JPS63224335A (en) | 1988-09-19 |
| JPH057865B2 JPH057865B2 (en) | 1993-01-29 |
Family
ID=13085844
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62058489A Granted JPS63224335A (en) | 1987-03-13 | 1987-03-13 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63224335A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2014011227A (en) * | 2012-06-28 | 2014-01-20 | Sumitomo Electric Ind Ltd | Semiconductor device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60234335A (en) * | 1984-05-08 | 1985-11-21 | Toshiba Corp | Semiconductor device |
-
1987
- 1987-03-13 JP JP62058489A patent/JPS63224335A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60234335A (en) * | 1984-05-08 | 1985-11-21 | Toshiba Corp | Semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2014011227A (en) * | 2012-06-28 | 2014-01-20 | Sumitomo Electric Ind Ltd | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH057865B2 (en) | 1993-01-29 |
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