JPH10256467A - Silicon high frequency integrated circuit - Google Patents

Silicon high frequency integrated circuit

Info

Publication number
JPH10256467A
JPH10256467A JP5497597A JP5497597A JPH10256467A JP H10256467 A JPH10256467 A JP H10256467A JP 5497597 A JP5497597 A JP 5497597A JP 5497597 A JP5497597 A JP 5497597A JP H10256467 A JPH10256467 A JP H10256467A
Authority
JP
Japan
Prior art keywords
silicon
integrated circuit
frequency integrated
silicon substrate
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5497597A
Other languages
Japanese (ja)
Inventor
Masayuki Adachi
誠幸 足立
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Japan Radio Co Ltd
Original Assignee
Japan Radio Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Japan Radio Co Ltd filed Critical Japan Radio Co Ltd
Priority to JP5497597A priority Critical patent/JPH10256467A/en
Publication of JPH10256467A publication Critical patent/JPH10256467A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view
    • H01L2224/05554Shape in top view being square
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49175Parallel arrangements

Abstract

PROBLEM TO BE SOLVED: To provide an inductor, a capacitor, etc., high in Q of a circuit element using a silicon substrate, by electrically connecting a first silicon substrate high in specific resistance and a second silicon substrate low in specific resistance. SOLUTION: A transistor TR1 and resistors R1, R2, and R3 not requiring high Q are made by conventional silicon high frequency integrated circuit process, and inductors L1 and L2 and capacitors C1 and C2 requiring high Q are made in a separate high-resistance silicon substrate. Then, both silicon substrates are connected with each other, using a mounting technique such as a chip-on- chip technique, a multichip module technique, or the like, and they are accommodated in the same package, whereby a silicon high-frequency integrated circuit is constituted. Accordingly, the area of the silicon chip made of high-resistance silicon can be small by minimizing the size of the portion, where high Q is required, of the high-resistance silicon substrate.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、シリコン基板を用
いた高周波集積回路に関する。
The present invention relates to a high-frequency integrated circuit using a silicon substrate.

【0002】[0002]

【従来の技術】無線機器等の小型、軽量化が要求される
中で、高周波回路の集積回路化は不可欠のものとなって
いる。従来の高周波集積回路としては、ガリウム砒素に
よるMMIC(マイクロ波モノシリック集積回路)があ
る。しかしガリウム砒素基板はシリコン基板よりも高価
なため、集積回路の価格が高くなるという問題点があ
る。したがって、シリコン基板での高周波集積回路の実
現が望まれている。
2. Description of the Related Art With the demand for smaller and lighter wireless devices and the like, it has become essential to integrate high-frequency circuits into integrated circuits. Conventional high-frequency integrated circuits include gallium arsenide MMICs (microwave monolithic integrated circuits). However, since the gallium arsenide substrate is more expensive than the silicon substrate, there is a problem that the price of the integrated circuit increases. Therefore, realization of a high-frequency integrated circuit on a silicon substrate is desired.

【0003】図4に、従来の技術によるシリコン高周波
集積回路を用いたRFアンプを例示する。図4に示すよ
うに、集積回路化が実現できているのはトランジスタ、
バイアス回路からなるシリコン高周波集積回路22であ
って、入力整合回路21および出力整合回路23はシリ
コン上の回路素子のQ(クオリティファクタ)が低い等
の問題により、ディスクリート部品で外付け回路として
構成されている。
FIG. 4 illustrates an RF amplifier using a conventional silicon high-frequency integrated circuit. As shown in FIG. 4, the transistors that can be integrated are transistors,
A silicon high-frequency integrated circuit 22 comprising a bias circuit, wherein the input matching circuit 21 and the output matching circuit 23 are formed as discrete circuits by discrete components due to problems such as low Q (quality factor) of circuit elements on silicon. ing.

【0004】[0004]

【発明が解決しようとする課題】シリコン高周波集積回
路は、シリコン基板に導電性があるため、スパイラル構
造のインダクタ等の素子のQが低くなるほか、コンデン
サの対基板静電容量が生じてしまう等の問題点がある。
In a silicon high-frequency integrated circuit, since the silicon substrate has conductivity, the Q of an element such as an inductor having a spiral structure is reduced, and the capacitance of a capacitor to a substrate is generated. There is a problem.

【0005】このため、従来のシリコン高周波集積回路
では上記のようにトランジスタ、抵抗、コンデンサで構
成されており、インダクタを用いる入力整合回路および
出力整合回路が内蔵されることがなかった。
Therefore, the conventional silicon high-frequency integrated circuit is composed of the transistor, the resistor, and the capacitor as described above, and the input matching circuit and the output matching circuit using the inductor are not built in.

【0006】また、最近においては、比抵抗の高いシリ
コン基板を用いて基板の抵抗を高くし、インダクタ等の
素子のQを改善したシリコン高周波集積回路が報告され
ている。
In recent years, there has been reported a silicon high-frequency integrated circuit in which a silicon substrate having a high specific resistance is used to increase the resistance of the substrate and improve the quality factor of an element such as an inductor.

【0007】しかしながら、この場合においては、シリ
コン基板の比抵抗を高くすることで、新たに集積回路化
プロセスの開発が必要となるという問題点がある。
However, in this case, there is a problem that a new integrated circuit process needs to be developed by increasing the specific resistance of the silicon substrate.

【0008】また、新たに集積回路化プロセスを開発す
るにしても、高周波特性のよいトランジスタ素子も同時
に形成しなければならないので、基板の比抵抗をある程
度以上は大きくできないという問題点がある。
Further, even if a new integrated circuit process is developed, a transistor element having good high-frequency characteristics must be formed at the same time, so that there is a problem that the specific resistance of the substrate cannot be increased to a certain degree or more.

【0009】本発明は、シリコン基板を用いたプロセス
で回路素子のQが高いインダクタやコンデンサ等を実現
し、この素子を用いたシリコン高周波集積回路を提供す
ることを目的とする。
SUMMARY OF THE INVENTION It is an object of the present invention to realize an inductor or a capacitor having a high Q of a circuit element by a process using a silicon substrate, and to provide a silicon high-frequency integrated circuit using the element.

【0010】[0010]

【課題を解決するための手段】本発明にかかるシリコン
高周波集積回路は、高いQが要求される回路素子を形成
した比抵抗の高い第1のシリコン基板と、高いQが要求
されない回路素子を形成した比抵抗の低い第2のシリコ
ン基板とを備え、第1のシリコン基板と第2のシリコン
基板とを電気的に接続して構成したことを特徴とする。
According to the present invention, there is provided a silicon high-frequency integrated circuit comprising a first silicon substrate having a high specific resistance on which a circuit element requiring a high Q is formed, and a circuit element not requiring a high Q. And a second silicon substrate having a low specific resistance, wherein the first silicon substrate and the second silicon substrate are electrically connected to each other.

【0011】本発明にかかるシリコン高周波集積回路で
は、従来のシリコン高周波集積回路プロセスでトランジ
スタ、抵抗等の高いQが要求されない回路素子が形成さ
れ、別の高抵抗シリコン基板を用いてインダクタ、キャ
パシタ等の高いQが要求される回路素子が形成されて、
2つのシリコンプロセスを独自で最適化できるために、
同一の基板上にすべての素子を形成するシリコン高周波
集積回路よりも高性能な電気的特性が得られる。
In the silicon high frequency integrated circuit according to the present invention, a circuit element such as a transistor and a resistor which does not require high Q is formed by a conventional silicon high frequency integrated circuit process, and an inductor, a capacitor, etc. are formed by using another high resistance silicon substrate. Circuit elements that require a high Q of
Because the two silicon processes can be optimized independently,
Higher-performance electrical characteristics can be obtained than a silicon high-frequency integrated circuit in which all elements are formed on the same substrate.

【0012】また、本発明にかかるシリコン高周波集積
回路において、第1のシリコン基板に整合回路を形成し
てもよい。整合回路を構成するインダクタおよびキャパ
シタには高いQが要求されるが、これに対応することが
できる。
In the silicon high frequency integrated circuit according to the present invention, a matching circuit may be formed on the first silicon substrate. A high Q is required for the inductor and the capacitor constituting the matching circuit, which can cope with this.

【0013】また、本発明にかかるシリコン高周波集積
回路において、第1および第2のシリコン基板をチップ
オンチップして電気的に接続して、1つのパッケージと
してもよく、第1および第2のシリコン基板をマルチチ
ップモジュールとして電気的に接続して、1つのパッケ
ージとしてもよい。このようにすることで、外見上は今
までのシリコン高周波集積回路と同一になり、取り扱い
が容易になる。
In the silicon high-frequency integrated circuit according to the present invention, the first and second silicon substrates may be chip-on-chip and electrically connected to form a single package. The substrates may be electrically connected as a multi-chip module to form a single package. By doing so, the appearance is the same as the conventional silicon high frequency integrated circuit, and the handling becomes easy.

【0014】[0014]

【発明の実施の形態】本発明にかかるシリコン高周波集
積回路を実施の一形態によって説明する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS A silicon high-frequency integrated circuit according to the present invention will be described with reference to an embodiment.

【0015】図1は本発明の実施の一形態にかかるシリ
コン高周波集積回路の構成を示すブロック図であり、無
線通信機の高周波回路であるRF増幅器(アンプ)の例
である。
FIG. 1 is a block diagram showing a configuration of a silicon high-frequency integrated circuit according to an embodiment of the present invention, and is an example of an RF amplifier (amplifier) that is a high-frequency circuit of a wireless communication device.

【0016】図1は本発明の実施の一形態にかかるシリ
コン高周波集積回路を用いたRFアンプの構成を示す。
図2(A)、(B)および図3は比抵抗の高いシリコン
基板からなるシリコンチップと比抵抗の低いシリコン基
板からなるシリコンチップを電気的に接続する例を示
す。
FIG. 1 shows the configuration of an RF amplifier using a silicon high-frequency integrated circuit according to an embodiment of the present invention.
FIGS. 2A, 2B and 3 show an example in which a silicon chip formed of a silicon substrate having a high specific resistance and a silicon chip formed of a silicon substrate having a low specific resistance are electrically connected.

【0017】図1に示した本発明の実施の一形態にかか
るシリコン高周波集積回路を用いたRFアンプ1は、バ
イポーラのトランジスタTR1、トランジスタTR1に
バイアス電圧、バイアス電流を供給するバイアス回路
2、入力整合回路3、出力整合回路4で構成される。高
周波帯の信号の増幅を行うためには、トランジスタTR
1の入力端子側および出力端子側でインピーダンス整合
が必要となる。
The RF amplifier 1 using the silicon high-frequency integrated circuit according to the embodiment of the present invention shown in FIG. 1 includes a bipolar transistor TR1, a bias circuit 2 for supplying a bias voltage and a bias current to the transistor TR1, and an input. It comprises a matching circuit 3 and an output matching circuit 4. In order to amplify a high frequency band signal, the transistor TR
1, impedance matching is required on the input terminal side and the output terminal side.

【0018】シリコン高周波集積回路を用いたRFアン
プ1では、トランジスタTR1と、L型接続のインダク
タL1とキャパシタC1からなり信号源から出力される
信号をトランジスタTR1に供給すると共に、信号源の
出力インピーダンスとトランジスタTR1の入力インピ
ーダンスとのインピーダンス整合のための入力整合回路
3と、抵抗R1、R2、R3と高周波信号に対するデカ
ップリングコンデンサC3とからなりトランジスタTR
1に所定のバイアス電圧を印加するバイアス回路2と、
L型接続のインダクタL2とキャパシタC2からなりト
ランジスタTR1のコレクタ出力電圧が供給されてトラ
ンジスタTR1の出力インピーダンスと負荷インピーダ
ンスとのインピーダンス整合のための出力整合回路4と
からなっている。
In the RF amplifier 1 using a silicon high-frequency integrated circuit, a signal output from a signal source comprising a transistor TR1, an inductor L1 connected in an L-type, and a capacitor C1 is supplied to the transistor TR1, and the output impedance of the signal source is changed. An input matching circuit 3 for impedance matching between the transistor TR1 and the input impedance of the transistor TR1, and resistors R1, R2, R3 and a decoupling capacitor C3 for high-frequency signals.
A bias circuit 2 for applying a predetermined bias voltage to 1;
It comprises an L-connected inductor L2 and a capacitor C2, to which a collector output voltage of the transistor TR1 is supplied, and an output matching circuit 4 for impedance matching between the output impedance of the transistor TR1 and the load impedance.

【0019】ここで、入力整合回路3および出力整合回
路4は比抵抗の高いシリコン基板からなるシリコンチッ
プ11上に形成し、バイアス回路2およびトランジスタ
TR1は比抵抗の低いシシリコン基板からなるシリコン
チップ12上に形成して、1つのパッケージ内で2つの
シリコンチップ11、12を電気的に接続して、シリコ
ン高周波集積回路を構成する。
Here, the input matching circuit 3 and the output matching circuit 4 are formed on a silicon chip 11 made of a silicon substrate having a high specific resistance, and the bias circuit 2 and the transistor TR1 are formed on a silicon chip 12 made of a silicon substrate having a low specific resistance. The two silicon chips 11 and 12 are electrically connected in one package to form a silicon high-frequency integrated circuit.

【0020】ここで、トランジスタTR1はバイポーラ
のトランジスタの場合を示しているがユニポーラのトラ
ンジスタであってもよい。
Although the transistor TR1 is a bipolar transistor, it may be a unipolar transistor.

【0021】比抵抗の高いシリコン基板からなるシリコ
ンチップ11と比抵抗の低いシリコン基板からなるシリ
コンチップ12を電気的に接続する例を図2(A)およ
び図2(B)に示す。図2(A)は模式平面図を、図2
(B)は模式断面図を示す。
FIGS. 2A and 2B show an example in which a silicon chip 11 made of a silicon substrate having a high specific resistance and a silicon chip 12 made of a silicon substrate having a low specific resistance are electrically connected. FIG. 2A is a schematic plan view, and FIG.
(B) shows a schematic sectional view.

【0022】この例では、シリコンチップ11とシリコ
ンチップ12とはバンプ14a〜14dによって電気的
に接続し、シリコンチップ11からボンディングワイヤ
13a〜13dによってリード端子と接続するチップオ
ンチップ実装技術によって接続する例を示している。こ
のように構成したRFアンプ1をリードフレーム10に
搭載してパッケージに収納すれば、外見上は今までのシ
リコン高周波集積回路の場合と同一となり、取り扱いが
容易になる。
In this example, the silicon chip 11 and the silicon chip 12 are electrically connected by the bumps 14a to 14d, and are connected by the chip-on-chip mounting technique of connecting the silicon chip 11 to the lead terminals by the bonding wires 13a to 13d. An example is shown. If the RF amplifier 1 thus configured is mounted on the lead frame 10 and housed in a package, the appearance is the same as that of the conventional silicon high-frequency integrated circuit, and the handling becomes easy.

【0023】この場合、シリコンチップ11とシリコン
チップ12のいずれか一方をマザーチップまたはドータ
チップとしてもよい。
In this case, one of the silicon chip 11 and the silicon chip 12 may be a mother chip or a daughter chip.

【0024】次に、シリコンチップ11とシリコンチッ
プ12を電気的に接続する他の例を図3に示す。
Next, another example of electrically connecting the silicon chip 11 and the silicon chip 12 is shown in FIG.

【0025】図3に示すように、シリコンチップ11と
シリコンチップ12とはボンディングワイヤ15a〜1
5dによって電気的に接続し、シリコンチップ11、1
2からボンディングワイヤ13a〜13dによってリー
ド端子と接続するマルチチップモジュール実装技術で電
気的に接続してもよい。さらには、図3に示すように、
これをリードフレームに搭載してパッケージに収納すれ
ば、外見は今までと全く同一となり、取り扱いが容易に
なる。
As shown in FIG. 3, the silicon chips 11 and 12 are connected to bonding wires 15a to 15a.
5d, the silicon chips 11, 1
2, the connection may be made electrically by a multi-chip module mounting technique of connecting to lead terminals by bonding wires 13a to 13d. Further, as shown in FIG.
If this is mounted on a lead frame and stored in a package, the appearance will be exactly the same as before and handling will be easier.

【0026】上記した本発明の実施の一形態にかかるシ
リコン高周波集積回路において、整合回路を含むRFア
ンプ1の場合を例示したが、他の高周波回路についても
適用できることはいうまでもない。
In the silicon high-frequency integrated circuit according to the embodiment of the present invention described above, the case of the RF amplifier 1 including the matching circuit has been exemplified, but it is needless to say that the present invention can be applied to other high-frequency circuits.

【0027】次に、従来の場合と本発明の実施の一形態
にかかるシリコン高周波集積回路とを比較して説明す
る。
Next, the conventional case and the silicon high-frequency integrated circuit according to the embodiment of the present invention will be described in comparison.

【0028】従来のシリコン高周波集積回路プロセスに
用いられているシリコン基板の比抵抗は数10Ω・cm
程度である。このシリコン基板上にスパイラル構造のイ
ンダクタ等を形成すると素子のQは低くなる。
The specific resistance of the silicon substrate used in the conventional silicon high frequency integrated circuit process is several tens Ω · cm.
It is about. When a spiral-structured inductor or the like is formed on the silicon substrate, the Q of the element is reduced.

【0029】一方、比抵抗が大きい、数kΩ・cmオー
ダーの高抵抗シリコン基板を用いてスパイラル構造のイ
ンダクタ等を形成すると、ガリウム砒素基板で構成した
場合と同じ程度のQを有する回路素子、インダクタ等が
実現できる。
On the other hand, when an inductor or the like having a spiral structure is formed using a high-resistance silicon substrate having a large specific resistance and on the order of several kΩ · cm, a circuit element and an inductor having the same degree of Q as those formed by a gallium arsenide substrate are used. Etc. can be realized.

【0030】そこで、本発明の実施の一形態にかかるシ
リコン高周波集積回路では、Qの高いことが要求されな
いトランジスタTR1、抵抗R1、R2、R3を従来の
シリコン高周波集積回路プロセスで形成して、Qの高い
ことが要求されるインダクタL1、L2、キャパシタC
1、C2を別の高抵抗シリコン基板で形成する。そし
て、双方のシリコン基板をチップオンチップあるいはマ
ルチチップモジュール等の実装技術を用いて接続し、同
一パッケージに収納することで、シリコン高周波集積回
路を構成している。
Therefore, in the silicon high-frequency integrated circuit according to one embodiment of the present invention, the transistor TR1 and the resistors R1, R2, and R3, which do not need to have a high Q, are formed by a conventional silicon high-frequency integrated circuit process. Inductors L1 and L2 and capacitor C required to have high
1. C2 is formed on another high resistance silicon substrate. Then, both silicon substrates are connected by using a mounting technology such as a chip-on-chip or a multi-chip module, and are housed in the same package to constitute a silicon high-frequency integrated circuit.

【0031】現在のシリコン基板の大部分はC−MOS
プロセスで作製されており、C−MOSプロセスで使用
しているシリコン基板の比抵抗は、1〜20Ω・cmが
一般的である。したがって、高抵抗のシリコン基板は高
価なものとなる。しかるに本発明の実施の一形態にかか
るシリコン高周波集積回路のように、高抵抗シリコン基
板のサイズを高いQが要求される部分を最小限に抑える
ことによって、高抵抗シリコン基板からなるシリコンチ
ップ11の面積は少なくてすみ、低抵抗のシリコン基板
からなるシリコンチップ12と高抵抗シリコン基板から
なるシリコンチップ11とを電気的に接続する方が、全
てを高抵抗シリコン基板からなるシリコンチップ11で
作製するよりも安価になるという効果がある。
Most of the current silicon substrates are C-MOS
The specific resistance of a silicon substrate manufactured by a process and used in a C-MOS process is generally 1 to 20 Ω · cm. Therefore, a high-resistance silicon substrate is expensive. However, as in the silicon high-frequency integrated circuit according to the embodiment of the present invention, the size of the high-resistance silicon substrate is minimized to a portion where a high Q is required, so that the silicon chip 11 made of the high-resistance silicon substrate is reduced. The area is small, and when the silicon chip 12 made of a low-resistance silicon substrate and the silicon chip 11 made of a high-resistance silicon substrate are electrically connected, the whole is made of the silicon chip 11 made of a high-resistance silicon substrate. This has the effect of being cheaper than that.

【0032】入力信号の周波数が変わったとしても、本
発明の実施の一形態にかかるシリコン高周波集積回路の
構成を用いることによって、整合回路3、4のシリコン
チップ11のみを変更することで対応することができ
る。この結果、シリコン高周波集積回路の汎用性が向上
するという効果も得られる。
Even if the frequency of the input signal changes, it can be handled by changing only the silicon chip 11 of the matching circuits 3 and 4 by using the configuration of the silicon high-frequency integrated circuit according to the embodiment of the present invention. be able to. As a result, the effect that the versatility of the silicon high-frequency integrated circuit is improved can be obtained.

【0033】また、シリコンチップを一体型で形成する
場合には、高抵抗のシリコン基板上の拡散条件が従来の
場合と異なる。このために新たなシリコン集積回路プロ
セスの開発の必要性が生じるが、本発明の実施の一形態
にかかるシリコン高周波集積回路では従来のプロセスが
そのまま使用できるという効果がある。
In the case where the silicon chip is formed integrally, the diffusion conditions on the high-resistance silicon substrate are different from those in the conventional case. This necessitates the development of a new silicon integrated circuit process, but the silicon high-frequency integrated circuit according to one embodiment of the present invention has the effect that the conventional process can be used as it is.

【0034】さらにいえば、従来のシリコン集積回路プ
ロセスにおいては、コレクタ抵抗を低減するためにNタ
イプの埋込層と素子間を分離するためにPタイプのアイ
アソレーションをサブストレート上に形成する。また、
サブストレートからエピタキシャル層への再拡散も生じ
る。従来のシリコン集積回路プロセスはこれらの拡散条
件が最適化されて完成している。しかるに、サブストレ
ートの比抵抗を高くするとこれらの条件を最適化しなけ
ればならない。仮に新たな条件を求めるとしても、比抵
抗が高くなると拡散が広がるので、トランジスタの微細
化には有利の方向ではない。
Furthermore, in the conventional silicon integrated circuit process, a P-type isolation is formed on the substrate to separate the N-type buried layer from the device in order to reduce the collector resistance. Also,
Re-diffusion from the substrate to the epitaxial layer also occurs. The conventional silicon integrated circuit process is completed by optimizing these diffusion conditions. However, if the specific resistance of the substrate is increased, these conditions must be optimized. Even if a new condition is obtained, the diffusion increases as the specific resistance increases, which is not an advantageous direction for miniaturization of the transistor.

【0035】一方、インダクタL1、L2、キャパシタ
C1、C2等のQを高くするために、配線の厚さを厚く
して直列抵抗を低くすることも考えられる。しかし従来
のシリコン集積回路プロセスで配線の厚さを厚くしよう
とすると、平坦性の問題など制約要因が生じる。
On the other hand, in order to increase the Q of the inductors L1 and L2, the capacitors C1 and C2, it is conceivable to increase the thickness of the wiring and reduce the series resistance. However, if the thickness of the wiring is increased in the conventional silicon integrated circuit process, there are constraints such as a problem of flatness.

【0036】しかるに本発明の実施の一形態にかかるシ
リコン高周波集積回路によれば、インダクタL1、L
2、キャパシタC1、C2等の高いQを要求される素子
を別のシリコン基板のチップにすることによって、比抵
抗の高いシリコンチップ11と比抵抗の低いシリコンチ
ップ12との作製のためのシリコン集積回路プロセスは
それぞれ独自に最適化することができて、従来のシリコ
ンチップを一体型で形成する場合に生ずる上記したシリ
コン集積回路プロセスの制約事項がなくなり、配線の厚
さを厚くしたり、配線工程を変えたりすることが可能と
なる効果が得られる。
However, according to the silicon high-frequency integrated circuit according to the embodiment of the present invention, the inductors L1 and L
2. By integrating elements requiring high Q, such as the capacitors C1 and C2, into chips of another silicon substrate, silicon integration for manufacturing a silicon chip 11 having a high specific resistance and a silicon chip 12 having a low specific resistance is performed. The circuit process can be independently optimized, eliminating the above-mentioned restrictions of the silicon integrated circuit process that occur when a conventional silicon chip is formed as an integrated type, and increasing the wiring thickness and the wiring process. Or the like can be changed.

【0037】さらに、従来のシリコン集積回路プロセス
でキャパシタを形成した場合、キャパシタの電極に接続
される、寄生抵抗と寄生コンデンサとの直列寄生素子が
生ずる。この寄生抵抗はサブストレートによるものであ
る。しかるに、本発明の実施の一形態にかかるシリコン
高周波集積回路におけるようにキャパシタが形成される
シリコン基板の比抵抗を高くすることによって寄生抵抗
の抵抗値は大きくなって、キャパシタに対する寄生素子
の影響が低減されるという効果も得られる。
Further, when a capacitor is formed by a conventional silicon integrated circuit process, a series parasitic element of a parasitic resistance and a parasitic capacitor connected to the electrode of the capacitor occurs. This parasitic resistance is due to the substrate. However, as in the silicon high-frequency integrated circuit according to the embodiment of the present invention, by increasing the specific resistance of the silicon substrate on which the capacitor is formed, the resistance value of the parasitic resistance increases, and the influence of the parasitic element on the capacitor is reduced. The effect of reduction is also obtained.

【0038】さらにまた、本発明の実施の一形態にかか
るシリコン高周波集積回路におけるようにトランジスタ
が形成されるシリコン基板の比抵抗は高くされないた
め、上記したシリコン基板の比抵抗を高くした場合に生
ずるトランジスタの微細化が妨げられることもないとい
う効果も得られる。
Further, since the specific resistance of the silicon substrate on which the transistor is formed is not increased as in the silicon high-frequency integrated circuit according to the embodiment of the present invention, this occurs when the specific resistance of the silicon substrate is increased. The effect that the miniaturization of the transistor is not hindered is also obtained.

【0039】[0039]

【発明の効果】以上説明したように本発明にかかるシリ
コン高周波集積回路によれば、高いQが要求されるイン
ダクタ、キャパシタ等を比抵抗の高いシリコン基板に生
成し、高周波特性のよいトランジスタ等を比抵抗が従来
通りのシリコン基板に生成し、比抵抗の異なるシリコン
基板からなる2つのシリコンチップをチップオンチッ
プ、もしくはマルチチップモジュール等の実装技術を用
いて接続し、1つのパッケージに収納することによっ
て、回路素子のQが高い整合回路等を内蔵したシリコン
高周波集積回路となり、従来の集積回路と同様に使用す
ることができるという効果が得られる。
As described above, according to the silicon high-frequency integrated circuit of the present invention, an inductor, a capacitor, etc., which require a high Q, are formed on a silicon substrate having a high specific resistance, and a transistor, etc., having good high-frequency characteristics are formed. A specific resistance is generated on a conventional silicon substrate, and two silicon chips composed of silicon substrates having different specific resistances are connected using a mounting technology such as a chip-on-chip or a multi-chip module and stored in one package. As a result, a silicon high frequency integrated circuit having a built-in matching circuit or the like having a high Q of the circuit element can be obtained, and it can be used similarly to a conventional integrated circuit.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の実施の一形態にかかるシリコン高周波
集積回路の構成を示すブロック図である。
FIG. 1 is a block diagram showing a configuration of a silicon high-frequency integrated circuit according to an embodiment of the present invention.

【図2】本発明の実施の一形態にかかるシリコン高周波
集積回路を構成する比抵抗の高いシリコンチップと比抵
抗の低いシリコンチップを電気的に接続するときの説明
図である。
FIG. 2 is an explanatory diagram when a silicon chip having a high specific resistance and a silicon chip having a low specific resistance constituting the silicon high-frequency integrated circuit according to one embodiment of the present invention are electrically connected;

【図3】本発明の実施の一形態にかかるシリコン高周波
集積回路を構成する比抵抗の高いシリコンチップと比抵
抗の低いシリコンチップを電気的に接続するときの他の
説明図である。
FIG. 3 is another explanatory diagram when a silicon chip having a high specific resistance and a silicon chip having a low specific resistance that constitute the silicon high-frequency integrated circuit according to the embodiment of the present invention are electrically connected.

【図4】従来のシリコン高周波集積回路の構成を示すブ
ロック図である。
FIG. 4 is a block diagram showing a configuration of a conventional silicon high-frequency integrated circuit.

【符号の説明】[Explanation of symbols]

1 RFアンプ 2 バイアス回路 3 入力整合回路 4 出力整合回路 11、12 シリコンチップ 13a〜13d、15a〜15d ボンディングワイヤ 14a〜14d バンプ C1、C2 キャパシタ C3 デカップリングコンデンサ L1、L2 インダクタ R1、R2、R3 抵抗 TR1 トランジスタ DESCRIPTION OF SYMBOLS 1 RF amplifier 2 Bias circuit 3 Input matching circuit 4 Output matching circuit 11, 12 Silicon chip 13a-13d, 15a-15d Bonding wire 14a-14d Bump C1, C2 Capacitor C3 Decoupling capacitor L1, L2 Inductor R1, R2, R3 Resistance TR1 transistor

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】高いQが要求される回路素子を形成した比
抵抗の高い第1のシリコン基板と、高いQが要求されな
い回路素子を形成した比抵抗の低い第2のシリコン基板
とを備え、第1のシリコン基板と第2のシリコン基板と
を電気的に接続して構成したことを特徴とするシリコン
高周波集積回路。
A first silicon substrate having a high specific resistance on which a circuit element requiring a high Q is formed, and a second silicon substrate having a low specific resistance on which a circuit element not requiring a high Q is formed; 1. A silicon high-frequency integrated circuit, wherein a first silicon substrate and a second silicon substrate are electrically connected to each other.
【請求項2】請求項1記載のシリコン高周波集積回路に
おいて、第1のシリコン基板に整合回路を形成したこと
を特徴とするシリコン高周波集積回路。
2. The silicon high-frequency integrated circuit according to claim 1, wherein a matching circuit is formed on the first silicon substrate.
【請求項3】請求項1記載のシリコン高周波集積回路に
おいて、第1および第2のシリコン基板をチップオンチ
ップして電気的に接続し、1つのパッケージとしたこと
を特徴とするシリコン高周波集積回路。
3. The silicon high-frequency integrated circuit according to claim 1, wherein the first and second silicon substrates are chip-on-chip and electrically connected to form a single package. .
【請求項4】請求項1記載のシリコン高周波集積回路に
おいて、第1および第2のシリコン基板をマルチチップ
モジュールとして電気的に接続して、1つのパッケージ
としたことを特徴とするシリコン高周波集積回路。
4. The silicon high-frequency integrated circuit according to claim 1, wherein the first and second silicon substrates are electrically connected as a multi-chip module to form a single package. .
JP5497597A 1997-03-10 1997-03-10 Silicon high frequency integrated circuit Pending JPH10256467A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5497597A JPH10256467A (en) 1997-03-10 1997-03-10 Silicon high frequency integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5497597A JPH10256467A (en) 1997-03-10 1997-03-10 Silicon high frequency integrated circuit

Publications (1)

Publication Number Publication Date
JPH10256467A true JPH10256467A (en) 1998-09-25

Family

ID=12985664

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5497597A Pending JPH10256467A (en) 1997-03-10 1997-03-10 Silicon high frequency integrated circuit

Country Status (1)

Country Link
JP (1) JPH10256467A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7088983B2 (en) 1999-02-03 2006-08-08 Rohm Co., Ltd. Semiconductor device for radio communication device, and radio communication device using said semiconductor device
CN114284390A (en) * 2021-12-23 2022-04-05 中国电子科技集团公司第四十四研究所 Vertical incidence ultra-wideband integrated photoelectric detector chip and manufacturing method thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7088983B2 (en) 1999-02-03 2006-08-08 Rohm Co., Ltd. Semiconductor device for radio communication device, and radio communication device using said semiconductor device
CN114284390A (en) * 2021-12-23 2022-04-05 中国电子科技集团公司第四十四研究所 Vertical incidence ultra-wideband integrated photoelectric detector chip and manufacturing method thereof
CN114284390B (en) * 2021-12-23 2024-04-16 中国电子科技集团公司第四十四研究所 Vertical incidence ultra-wideband integrated photoelectric detector chip and manufacturing method thereof

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