JPH057865B2 - - Google Patents

Info

Publication number
JPH057865B2
JPH057865B2 JP62058489A JP5848987A JPH057865B2 JP H057865 B2 JPH057865 B2 JP H057865B2 JP 62058489 A JP62058489 A JP 62058489A JP 5848987 A JP5848987 A JP 5848987A JP H057865 B2 JPH057865 B2 JP H057865B2
Authority
JP
Japan
Prior art keywords
lead wire
integrated circuit
pad
transmission line
length
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP62058489A
Other languages
Japanese (ja)
Other versions
JPS63224335A (en
Inventor
Takao Hasegawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP62058489A priority Critical patent/JPS63224335A/en
Publication of JPS63224335A publication Critical patent/JPS63224335A/en
Publication of JPH057865B2 publication Critical patent/JPH057865B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Description

【発明の詳細な説明】 ［産業上の利用分野］ この発明は半導体集積回路装置に関し、特に集
積回路チツプの電極パツドとパツケージの外部端
子との接続に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and more particularly to the connection between electrode pads of an integrated circuit chip and external terminals of a package.

［従来の技術］ 近年、GaAsFET、Siバイポーラトランジスタ
等を用いたUHF帯低雑音増幅器等の研究開発が
活発に行なわれている。特に、複数のFET、付
随する整合回路等を１つのチツプ上に構成するい
わゆるモノリシツク集積回路技術は、低コスト
性、高信頼性等の有利な特徴を持つので、様々な
デバイスへの応用が検討され、実用化されてい
る。[Prior Art] In recent years, research and development of UHF band low-noise amplifiers using GaAsFETs, Si bipolar transistors, etc. has been actively conducted. In particular, so-called monolithic integrated circuit technology, in which multiple FETs, associated matching circuits, etc. are configured on a single chip, has advantageous features such as low cost and high reliability, so its application to various devices is being considered. and has been put into practical use.

このような従来のモノリシツク集積回路におい
ては、整合回路等を製造段階でチツプ上に構成す
るので、チツプ完成後に所望の回路特性が得られ
なかつた場合には、回路を調整することが不可能
であつた。そこで従来は、設計を変更して所望の
特性が得られるまで試行錯誤を繰返す手法が多く
採用されていた。 In such conventional monolithic integrated circuits, matching circuits and the like are constructed on the chip at the manufacturing stage, so if the desired circuit characteristics cannot be obtained after the chip is completed, it is impossible to adjust the circuit. It was hot. Therefore, in the past, many methods have been adopted in which the design is changed and trial and error is repeated until the desired characteristics are obtained.

［発明が解決しようとする問題点］ 上記のように試行錯誤を繰返す手法の場合、多
くのチツプを個々に調整することになるので、コ
ストが嵩み、モノリシツク化の長所である低コス
ト性に反することとなり、モノリシツク化するこ
との意味がなくなつてしまうという問題点があつ
た。[Problems to be solved by the invention] In the case of the above-mentioned method of repeating trial and error, many chips must be adjusted individually, which increases the cost and makes it difficult to achieve low cost, which is the advantage of monolithic design. There was a problem in that the opposite was true, and there was no point in making it monolithic.

そこで、この発明は上記の問題点を解決するた
めになされたもので、チツプ完成後に整合回路を
微調整することが可能な半導体集積回路装置を提
供することを目的とする。 SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a semiconductor integrated circuit device in which a matching circuit can be finely adjusted after a chip is completed.

［問題点を解決するための手段］ この発明に係る半導体集積回路装置は、電極パ
ツドを有する集積回路チツプ、外部端子を有する
パツケージ、帯状の伝送線路からなる中継用パツ
ド、電極パツドと帯状の伝送線路の任意の位置と
の間に接続される第１のリード線、および外部端
子と帯状の伝送線路の任意の位置との間に接続さ
れる第２のリード線を備える。帯状の伝送線路
は、第１のリード線の接続位置および第２のリー
ド線の接続位置を変えることによつて第１のリー
ド線の長さおよび第２のリード線の長さをそれぞ
れ調整可能とするように、集積回路チツプの側部
に配置される。[Means for Solving the Problems] A semiconductor integrated circuit device according to the present invention includes an integrated circuit chip having an electrode pad, a package having an external terminal, a relay pad consisting of a strip-shaped transmission line, and an electrode pad and a strip-shaped transmission line. The transmission line includes a first lead wire connected to an arbitrary position on the transmission line, and a second lead wire connected between the external terminal and an arbitrary position on the belt-shaped transmission line. In the belt-shaped transmission line, the length of the first lead wire and the length of the second lead wire can be adjusted by changing the connection position of the first lead wire and the connection position of the second lead wire. It is placed on the side of the integrated circuit chip so that the

［作用］ 一般に集積回路のパツケージを行なう場合に
は、パツケージングによる寄生的回路要素の介在
を極力避けるように行なつている。また、集積回
路の入出力の直列インダクタンスは回路特性に影
響を与えるので、従来はこの影響を避けるため
に、集積回路チツプの電極パツドとパツケージの
外部端子とを接続するリード線の長さを極力短く
し、インダクタンスを小さくしていた。しかし、
この発明においては、この直列インダクタンスの
影響を積極的に利用し、リード線の長さを変える
ことを可能に構成し、リード線の長さを変えるこ
とによつて直列インダクタンスの大きさを変え、
回路の調整を行なうようにしている。[Operation] Generally, when packaging an integrated circuit, the intervention of parasitic circuit elements due to packaging is avoided as much as possible. In addition, since the series inductance of the input and output of an integrated circuit affects the circuit characteristics, conventionally, in order to avoid this effect, the length of the lead wire connecting the electrode pad of the integrated circuit chip and the external terminal of the package was minimized. It was made shorter and the inductance was reduced. but,
In this invention, the influence of this series inductance is actively utilized, the length of the lead wire can be changed, and by changing the length of the lead wire, the magnitude of the series inductance can be changed.
I am trying to adjust the circuit.

すなわち、この発明に係る半導体集積回路装置
においては、中継用パツドにおける第１のリード
線および第２のリード線を接続する位置を変える
ことによつて、リード線の長さを調整することが
でき、それによつて直列インダクタンスの大きさ
を調整することができる。 That is, in the semiconductor integrated circuit device according to the present invention, the length of the lead wire can be adjusted by changing the connecting position of the first lead wire and the second lead wire in the relay pad. , thereby allowing the magnitude of the series inductance to be adjusted.

［実施例］ 以下、この発明の実施例を図面を用いて説明す
る。[Examples] Examples of the present invention will be described below with reference to the drawings.

第１図はこの発明の一実施例である半導体集積
回路装置の構成を示す概略図である。 FIG. 1 is a schematic diagram showing the configuration of a semiconductor integrated circuit device according to an embodiment of the present invention.

図において、集積回路チツプ１上の所定位置に
は、入力パツド２および出力パツド３が設けられ
ている。そして、この集積回路チツプ１の外方に
は、パツケージの入力端子４および出力端子５が
位置している。この発明の半導体集積回路装置に
おいては、入力パツド２と入力端子４との間およ
び出力パツド３と出力端子５との間に、それぞれ
帯状の中継用パツド６，７が設けられている。 In the figure, an input pad 2 and an output pad 3 are provided at predetermined positions on an integrated circuit chip 1. An input terminal 4 and an output terminal 5 of the package are located outside the integrated circuit chip 1. In the semiconductor integrated circuit device of the present invention, strip-shaped relay pads 6 and 7 are provided between input pad 2 and input terminal 4 and between output pad 3 and output terminal 5, respectively.

この中継用パツド６，７は、低損失でかつ高特
性インピーダンスの伝送線路により形成されてい
る。入力パツド２と中継用パツド６とは第１のリ
ード線８によつて接続され、入力端子４と中継用
パツド６とは第２のリード線１０によつて接続さ
れる。また、出力パツド３と中継用パツド７とは
第１のリード線９によつて接続され、出力端子５
と中継用パツド７とは第２のリード線１１によつ
て接続される。 The relay pads 6 and 7 are formed of transmission lines with low loss and high characteristic impedance. The input pad 2 and the relay pad 6 are connected by a first lead wire 8, and the input terminal 4 and the relay pad 6 are connected by a second lead wire 10. Further, the output pad 3 and the relay pad 7 are connected by a first lead wire 9, and the output terminal 5
and the relay pad 7 are connected by a second lead wire 11.

第１のリード線８，９および第２のリード線１
０，１１は中継用パツド６，７の任意の位置に接
続することができ、接続する位置を変えることに
よつて、リード線の長さを任意に調整することが
できる。たとえば、リード線の長さを長くする場
合には、点線で示すように接続する。 First lead wires 8, 9 and second lead wire 1
0 and 11 can be connected to any position on the relay pads 6 and 7, and by changing the connection position, the length of the lead wire can be adjusted as desired. For example, when increasing the length of the lead wire, connect it as shown by the dotted line.

このようにリード線長を任意に調整することが
できるので、入出力各２本のリード線により、イ
ンダクタンスの大きさを任意に調整することがで
き、所望の特性が得られるように整合回路の微調
整を行なうことができる。 Since the length of the lead wires can be adjusted arbitrarily in this way, the size of the inductance can be adjusted arbitrarily by using two lead wires for each input and output, and the matching circuit can be adjusted to obtain the desired characteristics. Fine adjustments can be made.

第２図は、この発明の他の実施例の構成を示す
概略図である。 FIG. 2 is a schematic diagram showing the configuration of another embodiment of the invention.

図において、集積回路チツプ１上の入力パツド
２とパツケージの入力端子４とを接続するための
中継用パツド６は、蛇行するように形成された帯
状の伝送線路からなり、この中継用パツド６は伝
送線路用低損失基板１２上に形成されている。 In the figure, the relay pad 6 for connecting the input pad 2 on the integrated circuit chip 1 and the input terminal 4 of the package is composed of a belt-shaped transmission line formed in a meandering manner. It is formed on a low-loss substrate 12 for transmission line.

入力パツド２と中継用パツド６とは第１のリー
ド線８により接続され、入力端子４と中継用パツ
ド６とは第２のリード線１０により接続される。
中継用パツド６においてこれらの第１のリード線
８または第２のリード線１０を接続する位置ａ、
ｂ、ｃ、ｄ、ｅ、ｆ、ｇを変えることによつて、
第１の実施例の場合と同様に、リード線長を任意
に調整することができる。 The input pad 2 and the relay pad 6 are connected by a first lead wire 8, and the input terminal 4 and the relay pad 6 are connected by a second lead wire 10.
a position a where these first lead wires 8 or second lead wires 10 are connected in the relay pad 6;
By changing b, c, d, e, f, g,
As in the case of the first embodiment, the lead wire length can be adjusted arbitrarily.

この実施例の場合は、リード線を接続する位置
を一定させることができるので、リード線長の再
現性に優れている。 In the case of this embodiment, since the position where the lead wire is connected can be made constant, the reproducibility of the lead wire length is excellent.

なお、第２図の実施例においては、入力側しか
示していないが、出力側も同様にしてインダクタ
ンスの微調整をすることができる。 In the embodiment of FIG. 2, only the input side is shown, but the inductance can be finely adjusted in the same way on the output side.

［発明の効果］ 以上のようにこの発明によれば、集積回路チツ
プの電極パツドとパツケージの外部端子との間に
中継用パツドを設け、この中継用パツドにおいて
リード線を接続する位置を変えることによつて、
電極パツドと外部端子間のリード線長を調整し、
直列インダクタンスを調整することができる。し
たがつて、集積回路チツプ完成後の整合回路の微
調整が可能となる。[Effects of the Invention] As described above, according to the present invention, a relay pad is provided between the electrode pad of the integrated circuit chip and the external terminal of the package, and the position at which the lead wire is connected in this relay pad is changed. According to
Adjust the lead wire length between the electrode pad and external terminal,
Series inductance can be adjusted. Therefore, it is possible to fine-tune the matching circuit after the integrated circuit chip is completed.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図はこの発明による半導体集積回路装置の
一実施例を示す概略図、第２図は他の実施例を示
す概略図である。 図において、１は集積回路チツプ、２は入力パ
ツド、３は出力パツド、４は入力端子、５は出力
端子、６，７は中継用パツド、８，９は第１のリ
ード線、１０，１１は第２のリード線、１２は伝
送線路用低損失基板を示す。 FIG. 1 is a schematic diagram showing one embodiment of a semiconductor integrated circuit device according to the present invention, and FIG. 2 is a schematic diagram showing another embodiment. In the figure, 1 is an integrated circuit chip, 2 is an input pad, 3 is an output pad, 4 is an input terminal, 5 is an output terminal, 6 and 7 are relay pads, 8 and 9 are first lead wires, 10 and 11 12 indicates a second lead wire, and 12 indicates a low-loss substrate for a transmission line.

Claims (1)

【特許請求の範囲】[Claims] １ 電極パツドを有する集積回路チツプ、外部端
子を有するパツケージ、帯状の伝送線路からなる
中継用パツド、前記電極パツドと前記帯状の伝送
線路の任意の位置との間に接続される第１のリー
ド線、および前記外部端子と前記帯状の伝送線路
の任意の位置との間に接続される第２のリード線
を備え、前記帯状の伝送線路は、前記第１のリー
ド線の接続位置および前記第２のリード線の接続
位置を変えることによつて前記第１のリード線の
長さおよび前記第２のリード線の長さをそれぞれ
調整可能とするように、前記集積回路チツプの側
部に配置される、半導体集積回路装置。1. An integrated circuit chip having an electrode pad, a package having an external terminal, a relay pad consisting of a belt-shaped transmission line, and a first lead wire connected between the electrode pad and any position of the belt-shaped transmission line. , and a second lead wire connected between the external terminal and an arbitrary position of the belt-shaped transmission line, and the belt-shaped transmission line is connected between the connection position of the first lead wire and the second lead wire. arranged on the side of the integrated circuit chip so that the length of the first lead wire and the length of the second lead wire can be adjusted by changing the connection position of the lead wire. Semiconductor integrated circuit devices.
JP62058489A 1987-03-13 1987-03-13 Semiconductor integrated circuit device Granted JPS63224335A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62058489A JPS63224335A (en) 1987-03-13 1987-03-13 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62058489A JPS63224335A (en) 1987-03-13 1987-03-13 Semiconductor integrated circuit device

Publications (2)

Publication Number Publication Date
JPS63224335A JPS63224335A (en) 1988-09-19
JPH057865B2 true JPH057865B2 (en) 1993-01-29

Family

ID=13085844

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62058489A Granted JPS63224335A (en) 1987-03-13 1987-03-13 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPS63224335A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5991045B2 (en) * 2012-06-28 2016-09-14 住友電気工業株式会社 Semiconductor device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60234335A (en) * 1984-05-08 1985-11-21 Toshiba Corp Semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60234335A (en) * 1984-05-08 1985-11-21 Toshiba Corp Semiconductor device

Also Published As

Publication number Publication date
JPS63224335A (en) 1988-09-19

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