KR19990061140A - Pad Placement Method of Semiconductor Chip for Multichip Test - Google Patents

Abstract

The present invention relates to a method of arranging pads of a semiconductor chip for a multichip test. The pad arrangement method of the present invention allows the chip test pad and the bonding pad to be separated from each other, thereby enabling multi-chip testing during wafer testing. To this end, a plurality of pads are separately disposed on the long side and the short side of the semiconductor chip, and the plurality of pads disposed on the short side overlap with the pads disposed on the long side.

Description

Pad Placement Method of Semiconductor Chip for Multichip Test

The present invention relates to a method for arranging pads of a semiconductor chip for a multi-chip test. In particular, the method for arranging pads of a semiconductor chip enables multi-chip testing at the time of wafer testing by separately separating wafer pads and bonding pads. It is about.

In the conventional case, since the chip size for forming the semiconductor element was sufficient, multi-chip testing was possible even if the pads were arranged only on the long side (or short side) of the chip. However, due to the development of technology, the chip size is reduced, so that the width and spacing of the lead frame for packaging the chip are also shortened. For this reason, the lead frame design becomes very difficult by arranging the pad only on the long side (or short side) of the chip.

In order to solve this disadvantage, conventionally, a pad array is arranged by dispersing lead frames using both long and short sides of a chip. However, in this conventional case, manufacturing for multichip has been difficult due to the difficulty in arranging probe tips in producing a probe card required for testing chips on a wafer.

Hereinafter, this conventional problem will be described with reference to the drawings.

1 is a block diagram of a probe tip according to a conventional pad arrangement.

As shown, the probe tips are arranged up and down. Therefore, the multi-chip test can be multi-tested only in the horizontal direction. The reason will be explained with reference to FIG.

2 is a block diagram of a probe tip for multi-testing on a plurality of chips having a conventional pad arrangement.

As shown, in the case of the test arranged in the horizontal and vertical directions, for example, the probe tip (1) of the A chip and the probe tip (2) of the E chip are shorted, so that it is difficult to perform a normal test. . In this case, increasing the number in the horizontal direction allows more multi-chip tests, but in this case, the length of the signal line becomes longer, resulting in excessive noise, and therefore the number in the horizontal direction is inevitably limited.

The present invention is to solve the above problems, the wafer test pad and the bonding pad is formed by separating a part, the wafer test pad is disposed only on two symmetrical sides of the chip, the bonding pad is a long side and a short side of the chip The object of this invention is to provide the method of disperse | distributing and arrange | positioning to the.

1 is a block diagram of a probe tip for a chip having a conventional pad arrangement.

2 is a block diagram of a probe tip for multi-testing on a plurality of chips having a conventional pad arrangement.

3 is a schematic view of a probe tip for a chip arrangement of the pad according to the present invention;

4 is a block diagram of a probe tip for multi-testing on a plurality of chips having a pad arrangement according to the present invention.

5 is a plan view of a chip implementing the actual bonding using the pad arrangement according to the present invention.

Figure 6 is a circuit diagram showing the connection between the bonding pad and the test pad when the pad arrangement according to the present invention.

Explanation of symbols on the main parts of the drawings

1, 2: Probe Tips

3: wafer test pad

In order to achieve the above object of the present invention, a method for arranging a pad of a semiconductor chip for a multichip test in which a pad for multi-test for testing a wafer and a pad for bonding for bonding according to the present invention are divided and arranged. A plurality of pads are separately disposed on the long side and the short side of the chip, and the bonding pads overlapping some of the pads disposed on the long side are disposed on the short side of the semiconductor chip. Provided is a method of arranging pads of chips.

The pads overlapped with the long side and the short side are used for multi-test on the wafer. In addition, the pad disposed on the short side is used only as a bonding pad.

Of the plurality of pads overlapped with the long side and the short side, the pad disposed on the long side is used only for multi-test on the wafer.

Hereinafter, a method of arranging pads of a semiconductor chip for a multichip test according to the present invention will be described in detail with reference to the accompanying drawings.

3 is a schematic diagram of a probe tip for a chip according to the present invention.

As shown, the three pads on the left and right sides of the chip are located above the long side of the chip, the three pads on the left and bottom are below the long side, and the three pads on the top and top and bottom of the top and bottom sides. Since the three pads are arranged under the long side, only the pad on the long side is used for the wafer test, and all the pads are used as the bonding pads except for the plurality of pads 3 used for the wafer test during the package bonding. In other words, among pads of the same function that are overlapped on the short and long sides, the pad on the short side is used only as a bonding pad.

The three pads respectively disposed on the left and right upper sides of the short sides and the three pads respectively disposed on the lower left and right sides of the short sides are merely exemplary cases. Thus, if necessary, the number of pads to be allocated can be arbitrarily adjusted. In addition, although the semiconductor chip of FIG. 3 is assumed and assumed as a memory element, it can be applied to all integrated circuits other than the memory element.

A multichip test method for the semiconductor chip of FIG. 3 will be described with reference to FIG. 4.

4 is a block diagram of a probe tip for multi-testing a plurality of chips having a pad arrangement according to the present invention.

As shown, unlike the conventional case, when testing a large number of chips of FIG. 3 using a probe card, the shorting problem between the probe tip lines is not only solved, but also the multi in the horizontal and vertical directions. Test is possible.

5 is a plan view of a chip in which actual bonding is implemented using a pad arrangement according to the present invention.

As shown in FIG. 4, a pad of a short side that is not used in FIG. 4 is used during package bonding. For this reason, it is possible to have sufficient margin for the line width and line spacing of the lead frame at the time of packaging. In addition, pads having a function overlapping with the pads on the long side among the pads on the long side used in the wafer test are not used as the bonding pads.

The actual connection between the pads overlapping the long side and the short side will be described with reference to FIG. 6.

6 is a circuit diagram illustrating a connection relationship between a bonding pad and a test pad when the pad is disposed according to the present invention.

As shown, the test pad is connected to the internal circuit of the semiconductor chip through a fuse, and the bonding pad is directly connected to the internal circuit of the semiconductor chip. The fuse is cut by the wafer repair equipment after the multichip test is completed. Therefore, in the package, the input capacitance is not different from the conventional case. That is, the overall load on the external input signal is no different from the conventional case.

According to the method of the present invention described above, since the plurality of wafer test pads are arranged on the long side, the total number of pads increases. However, since the wafer test pad is only for testing, there is no reason to implement, for example, an input protection circuit for protecting the internal circuit of the semiconductor chip in connection with the test pad. It does not require area. In addition, an increase in input capacitance due to a plurality of connections is expected, but since the fuse of FIG. 6 is cut by the laser repair equipment when the wafer test is completed, it can be used without increasing the input capacitance in the actual package. That is, the overall load or pad charge area is virtually no difference from the conventional case.

According to the present invention, by partially separating the bonding pads and the test pads, multi-testing can be performed on the wafer, thereby significantly reducing the test cost of the wafer and lowering the overall production cost.

Claims (6)

In the pad arrangement method of a semiconductor chip for a multi-chip test in which the test pad for the wafer test and the bonding pad for bonding bonding are arranged separately, A plurality of pads are separately arranged on the long side and short side of the semiconductor chip, And a bonding pad overlapping some pads of the pads disposed on the long side at a short side of the semiconductor chip. The upper and lower pads of claim 1, wherein the upper and lower pads are located above the long side of the chip, the upper and lower pads are below the long side of the chip, and the upper and lower pads are above the long side of the chip. The pad is placed under the long side of the chip so that only the pad on the long side is used for wafer testing and all pads except for the pad on the long side overlapping the pad on the short side during wafer testing are used as bonding pads. Pad arrangement method of a semiconductor chip for a multi-chip test, characterized in that. The method of claim 1, wherein the pad disposed on the long side is used only as the multi test pad. 2. The method of claim 1, wherein the pads disposed on the long side of the pads disposed on the long side and the short side are used only for the multi-test on the wafer. The method of claim 4, wherein the multi test pad disposed at the long side and the internal circuit of the semiconductor chip are connected to each other by a fuse. The method of claim 5, wherein the fuse is cut after the multichip test is completed.